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Predicate encryption is a public-key encryption that supports attribute-hiding as well as payload-hiding and achieves high flexibility in terms of access control. Since Katz, Sahai, and Waters first proposed the predicate encryption scheme in 2008, several predicate encryption schemes have been published. Unfortunately these are impractical as they require O(n) pairing computations for decryption with considerably large sized public parameters, secret key, and ciphertext, where n is the dimension of the attribute/predicate vectors. In this paper, we propose a very efficient predicate encryption scheme that requires only n exponentiation plus three pairing computations for decryption with shorter sized public parameters, secret key, and ciphertext. The proposed scheme is proven selective attribute-secure against chosen-plaintext attacks in the standard model under the Asymmetric Decisional Bilinear Diffie-Hellman assumptions. [ABSTRACT FROM AUTHOR]

The growing demand on the performance of transparent computing systems requires good cache schemes in order to overcome the prolonged network latency. However, evaluating cache schemes, especially measuring the performance of a transparent computing system with particular cache scheme remains challenging. This is because neither method is available to evaluate the effectiveness and efficiency of the cache schemes in transparent computing, nor the simulator has been developed to measure the system performance under particular cache schemes. In this paper, we propose TranSim, a full-featured, high-performance simulation framework for transparent computing. For the first time, TranSim introduces a methodology to evaluate the performance of multi-level cache hierarchies in transparent computing under different cache configurations and cache replacement policies. TranSim can also demonstrate the behavior and performance of the entire transparent computing system rather than only the cache miss/hit rate. Using TranSim, the system designer can quickly evaluate the effectiveness of cache schemes along with the system performance. We construct several experiments to evaluate the effectiveness and efficiency of TranSim. Results show that TranSim can accurately output the performance of both the cache hierarchy and the entire transparent computing system. [ABSTRACT FROM AUTHOR]

Continuous scaling of process technology increases variations in transistors. The process variations cause large fluctuations in the access times of static random-access memory (SRAM) cells. Caches made of those SRAM cells cannot be accessed within the target clock cycle time, which reduces the yield of processors. Many schemes have been proposed to combat these access time failures in caches. However, these schemes are limited in their coverage and do not scale well at high failure rates. We propose a new level one (L1) cache architecture employing multi-cycle cell access (MCCA) and subarray-level parallel access (SLPA). MCCA eliminates all access-time failures in L1 caches. SLPA minimizes the performance impact of cache bandwidth loss due to MCCA. For further performance improvement, architectural techniques are proposed. Our experimental results show that our proposed L1 cache architecture incurs a performance hit of less than 1.2 percent compared to the conventional cache architecture with no access time failure. Our proposed architecture is not sensitive to access time failure rates and has a low overhead compared with previously proposed competitive schemes. [ABSTRACT FROM AUTHOR]

Buildings account for nearly 40 percent of the total energy consumption in the United States. As a critical step toward smart cities, it is essential to intelligently manage and coordinate the building operations to improve the efficiency and reliability of overall energy system. With the advent of smart meters and two-way communication systems, various energy consumptions from smart buildings can now be coordinated across the smart grid together with other energy loads and power plants. In this paper, we propose a comprehensive framework to integrate the operations of smart buildings into the energy scheduling of bulk power system through proactive building demand participation. This new scheme enables buildings to proactively express and communicate their energy consumption preferences to smart grid operators rather than passively receive and react to market signals and instructions such as time varying electricity prices. The proposed scheme is implemented in a simulation environment. The experiment results show that the proactive demand response scheme can achieve up to 10 percent system generation cost reduction and 20 percent building operation cost reduction compared with passive demand response scheme. The results also demonstrate that the system cost savings increase significantly with more flexible load installed and higher percentage of proactive customers participation level in the power network. [ABSTRACT FROM AUTHOR]

Audio represents one of the most appealing yet least exploited modalities in wireless sensor networks, due to the potentially extremely large data volumes and limited wireless capacity. Therefore, how to effectively collect audio sensing information remains a challenging problem. In this paper, we propose a new paradigm of audio information collection based on the concept of audio-on-demand. We consider a sink-free environment targeting for disaster management, where audio chunks are stored inside the network for retrieval. The difficulty is to guarantee a high search success rate without infrastructure support. To solve the problem, we design a novel replication algorithm that deploys an optimal number of O(\sqrtn) replicas across the sensor network. We prove the optimality of the energy consumption of the algorithm. We implement a sink-free audio-on-demand (SAoD) WSN system, and conduct extensive simulations to evaluate the performance and efficiency of our design. The experimental results show that our design can provide satisfactory quality of audio-on-demand service with short startup latency and slight playback jitter. Extensive simulation results show that this design achieves a search success rate of 98 percent while reducing the search energy consumption by an order of magnitude compared with existing schemes. [ABSTRACT FROM AUTHOR]

Even though 3D flash memory presents a grand opportunity to huge-capacity non-volatile memory, it suffers from serious program disturbance problems. In contrast to the past efforts in error correction codes and the work in trading the space utilization for reliability, we propose a disturbance-relaxation scheme that can alleviate the negative effects caused by program disturbance inside a physical block. This scheme does not introduce any extra overheads on encoding or storing of extra redundant data. In particular, a methodology is proposed to reduce the data error rate by distributing unavoidable disturbance errors to the flash-memory space of invalid data, with the considerations of the physical organization of 3D flash memory. A series of experiments was conducted based on real multi-layer 3D flash chips, and it showed that the proposed scheme could significantly enhance the reliability of 3D flash memory. [ABSTRACT FROM AUTHOR]

Dynamic random access memory (DRAM) requires periodic refresh operations to retain its data. In practice, DRAM retention times are normally distributed from 64 ms to several seconds. However, the conventional refresh method uses 64 ms as the refresh interval, since it applies the same refresh interval to all DRAM rows. Thus, the conventional refresh method results in unnecessary refresh operations (eventually, energy waste) to the DRAM rows whose retention times are longer than 64 ms. In this paper, we propose a practical refresh scheme that exploits refresh effect of DRAM read operations to reduce refresh overhead. Our proposed scheme applies a refresh interval longer than the conventional refresh interval (64 ms) to the DRAM chip. In this case, weak DRAM rows (DRAM rows whose retention times are shorter than the refresh interval of the DRAM chip) cannot retain their data. In order to retain the data stored in the weak DRAM rows, the memory controller issues read operations to the weak DRAM rows every required refresh interval for the weak DRAM rows. Our evaluation results show that our proposed scheme with 192 ms refresh interval reduces average refresh energy consumption up to 66.0 percent, which in turn reduces average DRAM energy consumption up to 31.8 percent, compared to the conventional refresh method (64 ms). Our proposed scheme requires no modification to internal DRAM chip structures, but it only adds a small weak row buffer (the buffer for the weak row information) to the memory controller, which has a negligible area overhead. [ABSTRACT FROM AUTHOR]

DDoS attack source traceback is an open and challenging problem. Deterministic packet marking (DPM) is a simple and effective traceback mechanism, but the current DPM based traceback schemes are not practical due to their scalability constraint. We noticed a factor that only a limited number of computers and routers are involved in an attack session. Therefore, we only need to mark these involved nodes for traceback purpose, rather than marking every node of the Internet as the existing schemes doing. Based on this finding, we propose a novel marking on demand (MOD) traceback scheme based on the DPM mechanism. In order to traceback to involved attack source, what we need to do is to mark these involved ingress routers using the traditional DPM strategy. Similar to existing schemes, we require participated routers to install a traffic monitor. When a monitor notices a surge of suspicious network flows, it will request a unique mark from a globally shared MOD server, and mark the suspicious flows with the unique marks. At the same time, the MOD server records the information of the marks and their related requesting IP addresses. Once a DDoS attack is confirmed, the victim can obtain the attack sources by requesting the MOD server with the marks extracted from attack packets. Moreover, we use the marking space in a round-robin style, which essentially addresses the scalability problem of the existing DPM based traceback schemes. We establish a mathematical model for the proposed traceback scheme, and thoroughly analyze the system. Theoretical analysis and extensive real-world data experiments demonstrate that the proposed traceback method is feasible and effective. [ABSTRACT FROM AUTHOR]

To guarantee reliability, bulk data dissemination relies on the negotiation scheme in which senders and receivers negotiate transmission schedule through a three-way handshake procedure. However, we find negotiation incurs a long dissemination time and seriously defers the network-wide convergence. On the other hand, the flooding approach, which is conventionally considered inefficient and energy-consuming, can facilitate bulk data dissemination if appropriately incorporated. This motivates us to pursue a delicate tradeoff between negotiation and flooding in the bulk data dissemination. We propose SurF (Survival of the Fittest), a bulk data dissemination protocol which adaptively adopts negotiation and leverages flooding opportunistically. SurF incorporates a time-reliability model to estimate the time efficiencies (flooding versus negotiation) and dynamically selects the fittest one to facilitate the dissemination process. We implement SurF in TinyOS 2.1.1 and evaluate its performance with 40 TelosB nodes. The results show that SurF, while retaining the dissemination reliability, reduces the dissemination time by 40 percent in average, compared with the state-of-the-art protocols. [ABSTRACT FROM AUTHOR]

Privacy protection is the primary concern when RFID applications are deployed in our daily lives. Due to the computational power constraints of passive tags, non-encryption-based singulation protocols have been recently developed, in which wireless jamming is used. However, the existing private tag access protocols without shared secrets rely on impractical physical layer assumptions, and thus they are difficult to deploy. To tackle this issue, we first redesign the architecture of RFID system by dividing an RF reader into two different devices, an RF activator and a trusted shield device (TSD). Then, we propose a novel coding scheme, namely Random Flipping Random Jamming (RFRJ), to protect tags’ content. Unlike the past work, the proposed singulation protocol utilizes only the physical layer techniques that are already implemented. Analyses and simulation results validate our distributed architecture with the RFRJ coding scheme, which defends tags’ privacy against various adversaries including the random guessing attack, correlation attack, ghost-and-leech attack, and eavesdropping. [ABSTRACT FROM AUTHOR]

Broadcast encryption (BE) schemes allow a sender to securely broadcast to any subset of members but require a trusted party to distribute decryption keys. Group key agreement (GKA) protocols enable a group of members to negotiate a common encryption key via open networks so that only the group members can decrypt the ciphertexts encrypted under the shared encryption key, but a sender cannot exclude any particular member from decrypting the ciphertexts. In this paper, we bridge these two notions with a hybrid primitive referred to as contributory broadcast encryption (ConBE). In this new primitive, a group of members negotiate a common public encryption key while each member holds a decryption key. A sender seeing the public group encryption key can limit the decryption to a subset of members of his choice. Following this model, we propose a ConBE scheme with short ciphertexts. The scheme is proven to be fully collusion-resistant under the decision $n$ -Bilinear Diffie-Hellman Exponentiation (BDHE) assumption in the standard model. Of independent interest, we present a new BE scheme that is aggregatable. The aggregatability property is shown to be useful to construct advanced protocols. [ABSTRACT FROM AUTHOR]

Today’s cloud data centers contain more than millions of servers and offer high bandwidth. A fundamental problem is how to significantly improve the large-scale system’s scalability to interconnect a large number of servers and meanwhile support various online services in cloud computing. One way is to deal with the challenge of potential mismatching between the network architecture and the data placement. To address this challenge, we present ANTELOPE, a scalable distributed data-centric scheme in cloud data centers, in which we systematically take into account both the property of network architecture and the optimization of data placement. The basic idea behind ANTELOPE is to leverage precomputation based data cube to support online cloud services. Since the construction of data cube suffers from the high costs of full materialization, we use a semantic-aware partial materialization solution to significantly reduce the operation and space overheads. Extensive experiments on real system implementations demonstrate the efficacy and efficiency of our proposed scheme. [ABSTRACT FROM PUBLISHER]

With the emergence of WiFi technology and network-based applications, the computing, communication and sensing capabilities of smartphones are increasing rapidly, and the smartphone has emerged as a particularly appealing platform for pervasive network applications. However, WiFi entails considerable energy consumption on these battery-powered devices. Finding ways to reduce power consumption on smartphones becomes a critical issue. In this paper, we propose an adaptive limit-rate selection algorithm based on anon-parametric signal strength prediction scheme and analyze its potential for energy savings. By periodically monitoring the received signal strength (RSS) in diverse network environments, the proposed scheme applies weighted scatter plot smoothing and kernel moving average algorithms to adaptively adjust file downloading and video streaming rates. Experimental results demonstrate that the proposed scheme can save 5.7% energy at least and 13.9% energy at most compared to non-adaptive and non-prediction schemes when the smartphone holders use the applications on the move. [ABSTRACT FROM PUBLISHER]

We propose algorithms for distributing the classifier rules to two ternary content addressable memories (TCAMs) and for incrementally updating the TCAMs. The performance of our scheme is compared against the prevalent scheme of storing classifier rules in a single TCAM in priority order. Our scheme results in an improvement in average lookup speed by up to 49% and an improvement in update performance by up to 3.84 times in terms of the number of TCAM writes. [ABSTRACT FROM AUTHOR]

This paper first envisions the advent of the wireless mesh networks with multiple radios and directional antennas in future. Then, based on the observation that simplicity induces efficiency and scalability, the paper proposes a joint geometric deployment and routing strategy for such mesh networks, and also gives a concrete approach under this strategy. The main idea of this strategy is to deploy mesh networks in certain kind of geometric graph, and then design a geometric routing protocol by exploiting the routing properties of this graph. The proposed concrete approach comprises two parts: (1) a topology generation algorithm based on Delaunay triangulations and (2) a geometric routing protocol based on the greedy forwarding algorithm. Both parts are characterized by simplicity and appealing properties, with formal proofs provided when possible. The simulation results validate our proposed approach. [ABSTRACT FROM AUTHOR]

On-chip photonic waveguides have been proposed as a feasible replacement for the long interconnects that cause speed and power bottlenecks. Along with recent advancements in nanophotonic technologies, we believe that combining on-chip waveguides with high-radix Network on Chip (NoC) topologies is a promising way to improve NoC performance. In this paper, we propose the BufferLess phOtonic ClOs Network (BLOCON) to exploit silicon photonics. We propose a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem, and a methodology to achieve an optimal off-chip laser-power budget. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and on-chip power performance of the compared electrical and photonic NoC architectures over synthetic traffic patterns and SPLASH-2 traces. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments. [ABSTRACT FROM AUTHOR]

This paper presents an efficient decomposition scheme for hardware-efficient realization of discrete cosine transform (DCT) based on distributed arithmetic. We have proposed an efficient design for the implementation of cyclic convolution based on a group distributed arithmetic (GDA) technique where the read-only memory size could be reduced over the existing GDA-based design. The proposed structure for DCT implementation, based on the new decomposition scheme and proposed design of GDA-based cyclic convolution, involves significantly less area complexity than the existing one. For example, to implement the DCT of transform length $(N = 17)$, the proposed design needs a lookup table of 128 words, while the existing design for $(N = 16)$ requires a lookup table of 256 words. From the synthesis results, it is found that proposed design involves significantly less area, gives higher throughput, and consumes less power compared to the existing designs of nearly the same or lower lengths. [ABSTRACT FROM PUBLISHER]

Given the multilevel internal SSD parallelism at the different four levels: channel-level, chip-level, die-level, and plane-level, how to exploit these levels of parallelism will directly and significantly impact the performance and endurance of SSDs, which is in turn primarily determined by three internal factors, namely, advanced commands, allocation schemes, and the priority order of exploiting the four levels of parallelism. In this paper, we analyze these internal factors to characterize their impacts, interplay, and parallelism for the purpose of performance and endurance enhancement of SSDs through an in-depth experimental study. We come to the following key conclusions: 1) Different advanced commands provided by Flash manufacturers exploit different levels of parallelism inside SSDs, where they can either improve or degrade the SSD performance and endurance depending on how they are used; 2) Different physical-page allocation schemes employ different advanced commands and exploit different levels of parallelism inside SSDs, giving rise to different performance and endurance impacts; 3) The priority order of using the four levels of parallelism has the most significant performance and endurance impact among the three internal factors. The optimal priority order of using the four levels of parallelism in SSDs is found to be: 1) the channel-level parallelism; 2) the die-level parallelism; 3) the plane-level parallelism; and 4) the chip-level parallelism. [ABSTRACT FROM PUBLISHER]

A wireless ad hoc network does not have an infrastructure, and thus, needs the cooperation of nodes in forwarding other nodes' packets. Reputation system is an effective approach to give nodes incentives to cooperate in packet forwarding. However, existing reputation systems either lack rigorous analysis, or have analysis in unrealistic models. In this paper, we propose FITS, the first reputation system that has rigorous analysis and guaranteed incentive compatibility in a practical model. FITS has two schemes: the first scheme is very simple, but needs a Perceived Probability Assumption (PPA); the second scheme uses more sophisticated techniques to remove the need for PPA. We show that both of these two FITS schemes have a subgame perfect Nash equilibrium in which the packet forwarding probability of every node is one. Experimental results verify that FITS provides strong incentives for nodes to cooperate. [ABSTRACT FROM AUTHOR]

Although many block replacement algorithms for buffer caches have been proposed to address the well-known drawbacks of the LRU algorithm, they are not robust and cannot maintain a consistent performance improvement over all workloads. This paper proposes a novel and simple replacement scheme, called the Robust Adaptive buffer Cache management schemE (RACE), which differentiates the locality of I/O streams by actively detecting access patterns that are inherently exhibited in two correlated spaces, that is, the discrete block space of program contexts from which I/O requests are issued and the continuous block space within files to which I/O requests are addressed. This scheme combines the global I/O regularities of an application and the local I/O regularities of individual files that are accessed in that application to accurately estimate the locality strength, which is crucial in deciding which blocks are to be replaced upon a cache miss. Through comprehensive simulations on 10 real-application traces, RACE is shown to have higher hit ratios than LRU and all other state-of-the-art cache management schemes studied in this paper. [ABSTRACT FROM AUTHOR]

Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce the memory footprint of embedded software, is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression, based on the concepts of static (using the static representation of the executable) and dynamic (using program execution traces) entropy and compare them with a state-of-the-art compression scheme, IBM's CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome of our work is that static compression is not directly related to bus traffic reduction, yet there is a trade off between static compression and dynamic compression, i.e., traffic reduction. [ABSTRACT FROM AUTHOR]

We study the information brokerage schemes in wireless sensor networks, which allow consumers to obtain data from producers by replicating and retrieving data in a certain set of sensors, and propose a novel information brokerage scheme, termed RDRIB. Unlike existing information brokerage schemes, RDRIB guarantees successful data retrieval without using any boundary detection algorithm and the geographic location information acquired by the global positioning system (GPS). In RDRIB, the double-ruling technique is used to replicate and retrieve the data within a constructed virtual boundary, and simulations show that RDRIB has good performance in terms of the replication memory overhead, the replication message overhead, the retrieval message overhead, the retrieval latency, and the construction message overhead. [ABSTRACT FROM PUBLISHER]