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Low power realization of high efficiency video coding (HEVC) standard, which has found widespread application in mobile devices, tablets, and high-definition televisions, calls for an efficient approximation of discrete cosine transform (DCT) technique. In this paper, a novel algorithm is proposed to determine the minimum number of low-frequency DCT coefficients required for transform and quantization block in HEVC. Moreover, it introduces hardware efficient 1-D architectures for 4, 8, 16, and 32-point DCT, that make use of the proposed algorithm and conform to the HEVC standard. When these architectures are extended to the HEVC test model (HM), it leads to a minor reduction of PSNR (<0.15 dB) and a slight increase in bitrate (<1.5%). The encoding time of HM encoder is reduced up to 16.02% and produces the rate-distortion performance comparable to the reference algorithm. A new memory efficient addressing scheme for transpose memory is presented for 2D-DCT. The proposed 2D-DCT architecture has a low power dissipation and energy consumption of 8.62 mW and 1.77 pJ respectively and can process at least sixty 8K ($7630\times 4830$) frames/s. Such architecture with low power and energy characteristics can be integrated into a real-time HEVC encoder for portable consumer electronic products. [ABSTRACT FROM AUTHOR]

Consumer electronics are expecting high-definition television (HDTV) services not only at home, but also in high-speed vehicles like cars, train, subways, etc. However, time domain synchronous OFDM (TDS-OFDM) could only provide HDTV services in static or low-speed channels, but not in fast fading channels due to the severe mutual interferences between the time-domain training sequence (TS) and the OFDM data block. Without changing the original TDS-OFDM signal structure, this paper firstly proposes the idea of regarding transmission parameter signaling (TPS) symbols embedded in the OFDM data block as frequency-domain pilots. This new perspective breaks the conventional concept that the training information of TDS-OFDM exists only in the time domain. Then, the two-dimensional channel estimation method jointly exploiting the time-domain TS as well as the frequency-domain pilots is proposed to improve the system reliability over fast fading channels. Simulation results demonstrate that reliable HDTV transmission could be achieved when the moving speed of consumer electronics is up to 120 km/h1. [ABSTRACT FROM PUBLISHER]

This paper presents the implementation process for an API that integrates interactive digital TV (iDTV) applications and home network (HN) services, mainly concerning issues of the Brazilian iDTV model. The research in this field is important because it represents current trends on the use of iDTV opening many business opportunities. With the convergence of service providers, modern communication technologies and consumer electronics devices at home, new iDTV applications have emerged, particularly those that use the set-top-boxes (or digital TV sets) processing power to provide additional services, which extends the possibilities of interaction between the user and the connected home. To implement this platform, a known model, which considers aspects of the Ginga middleware and the Open Services Gateway Initiative (OSGi) framework, was used. The idea behind the API model is to export service objects from one side to another, allowing the development of two types of applications: the first one on the Ginga-J machine and the last one on the Ginga-NCL machine. The main goals of this paper are (i) presenting the use of free tolls to perform such integration and (ii) showing the most relevant aspects in the core of the two models. Finally, a basic step-by-step process is shown in order to build integrated iDTVHN real applications using this platform. [ABSTRACT FROM PUBLISHER]

Constant bit-rate (CBR) encoding methods used for the real-time digital video applications such as terrestrial high definition television (HDTV) broadcasting often produce large picture quality fluctuation due to constraints on buffer size and buffering delay. In this paper, we propose a simple framelayer CBR encoding method which reduces large picture quality fluctuation of an encoded video under constant bit-rate and limited buffer size. We first define an intermediate encoder buffer level to be lower than the half of the maximum encoder buffer level. Then, the encoder buffer level is kept from being close to the maximum (or minimum) buffer level during encoding by slightly decreasing (or increasing) the number of bits estimated to encode each frame if the resulting buffer level becomes higher (or lower) than the intermediate buffer level. The experimental results show that the proposed CBR encoding method reduces the average local PSNR variation by 20.6% compared with previous CBR encoding method on average under constant bit-rate and limited buffer size. [ABSTRACT FROM PUBLISHER]

Super-resolution image reconstruction is an important technology in many image processing areas such as image sensing, medical imaging, satellite imaging, and television signal conversion. It is also being used as a unique selling point for a recent consumer HDTV set equipped with a multi-core processor. Among the various super-resolution methods, the learning-based method is one of the most promising solutions. However, this method is difficult to implement in real time because of the computational time required for searching the large database of reference images. In this paper, we propose a new learning-based superresolution method that utilizes total variation (TV) regularization. We obtain excellent image quality improvement and a large reduction in the computational time with this method. Our method was implemented on a multi-core processor to examine the possibility of real-time processing. The method enables the adoption of learning-based super-resolution for current HDTV sets equipped with multi-core processors as well as for the nextgeneration HDTVs with 4 K ? 2 K panels. [ABSTRACT FROM PUBLISHER]

This paper proposes a high-throughput LDPC (Low-Density Parity-Check) decoder architecture for DVB-S2, the second generation standard for European satellite digital video broadcasting system adopted for HDTV services. In the proposed decoder architecture, a unified processing module, B/CFM (Bitnode/Checknode Functional Module), is designed, which performs the computations both at bitnodes and at checknodes for maximal sharing of hardware resource. It performs the computations at bitnodes clustered into a group and at checknodes clustered also into a group sequentially. The B/CFMs replace the BFMs (Bitnode Functional Module) and CFMs (Checknode Functional Module) used in previous architecture, thus resulting to an increase in throughput. To support parallel data accesses by these B/CFMs, data aligner is designed and placed in front of input port of each memory bank. Experimental results of the proposed architecture exhibit the throughput of 1,020 Mbps, 95.8% improvements over previous architecture, with 25.2% increase in area. [ABSTRACT FROM AUTHOR]

This paper proposes a novel processing order and an efficient architecture for real-time implementation of the deblocking filter in H.264/A VC video coding standard. The process of the deblocking filter causes the intensive requirement of data and computations and increases the execution time of both encoding and decoding. The proposed processing order, double-cross processing order, is effectively constructed by a parallel flow to improve processing speed and reduce memory access. Moreover, the proposed architecture can save about 38- 80% of memory access as compared with other designs. Based on this high efficient architecture, the processing performance can be enhanced, and the operation frequency for standardized video specifications can be reduced. For the general video specification HDTV1080p (1920×1080 @30fps), the operation frequency of the proposed architecture is only 11.5 MHz. For the high resolution QFHD specification (3840×2160 @30fps), the operation frequency of the proposed architecture is only 46.6 MHz. The implementation result is about 20.14K gates, and the memory requirement is 64×32 bits. The power dissipation for QFHD specification is 7.7 m W at 46.6 MHz operating frequency. [ABSTRACT FROM AUTHOR]

In recent video applications such as MPEG or H.264/A VC, the bandwidth requirement for frame memory has become one of the most critical problems. Compressing pixel data before storing in off-chip frame memory is required to alleviate this problem. In this paper, we propose a lossless frame memory recompression scheme including 1) a lossless pixel compression algorithm, 2) an efficient address table organization method for random accessibility, and 3) frame memory placement scheme for compressed data to reduce the effective access time of SDRAM by suppressing row switching. Experimental results show that the proposed method reduces the frame data to 48% compared to that of the uncompressed one with H.264/A VC high profile encoder system, where 6.1kB of SRAM is required for the address table of full HD video. [ABSTRACT FROM AUTHOR]

The evaluation of liquid crystal display (LCD) quality in terms of human factors shows more accurate results than conventional measurements such as image resolution and response speed. In this paper, we propose a new method for measuring eyestrain based on pupil accommodation speed according to the change of four adjustment factors---brightness, contrast, saturation, and hue---of images on an LCD TV. Experimental results showed that the order of affecting the eyestrain much was the changes of hue, brightness, contrast and saturation. Based on them, the solutions for suppressing eyestrain of watchers of LCD TV are discussed. [ABSTRACT FROM AUTHOR]

In this paper, a tetrahedral interpolation technique is utilized to build new type architecture for real time color gamut mapping which has been known to be one of promising methods to enhance display quality of digital and/or high-definition TV. It is common practice to simple the required complex computations for the mapping by adopting three-dimensional interpolation techniques. If carefully arranged, the tetrahedral interpolation can be computed with simpler operations compared to the other types of interpolation such as a cubic or three-bilinear interpolation in the conventional reduced resolution look-up table. With these simplified operations, the proposed method reduces the required computational cost and the complexity of hardware implementation. The proposed method is implemented in VHDL code and the simulation results show that the proposed method reduces the number of gates needed to hardware implementation without loss of color reproduction quality. [ABSTRACT FROM AUTHOR]

This paper presents an HDTV video decoder core that is able to decode MPEG-2, MPEG-4 A VC and VC-I formats and is fully compatible with the Blu-ray Disc standard. The core has two major features which achieve low-cost hardware implementation for three different standards. First, a novel re-configurable architecture is adopted to realize reduced hardware for three different variable length coding tables. A hybrid architecture that consists of a cell array and coefficients memory is introduced By considering the trade-off between performance and cost, the cell array can compare a variable number of bits in a flexible manner. Second, a data compression method suitable for all video decoding standards is applied to reduce memory data usage and access bandwidth. A compression syntax based on Run-Level encoding with Exp-Golomb tables is used to achieve both low compression workload and reasonable memory cost. The core is implemented by top-down HDL basis approach, and the circuit volume is 1.5Mgates with 9Onm CMOS technology and operation clock.frequency is 162MHz for 1080i at 30fr/s. [ABSTRACT FROM AUTHOR]

Ultra-High Definition Television (U-HDTV) promises to offer a strong sense of reality to viewers by utilizing extremely high spatial and temporal resolution. In order to compress U-HDTV video sequences in a practical way, the video sequence is divided into sub-sequences and each sub-sequence is processed. However, the merged sequence of independently decoded sub-sequences inherently exhibits a distortion along the boundary of the sub-sequences, namely sub-sequence boundary distortion (SBD). In this paper, we first introduce a method to quantitatively measure the SBD. Then, we propose a post-processing algorithm that reduces the SBD. Experimental results indicate that the SBD is efficiently alleviated by the proposed post-processing algorithm. [ABSTRACT FROM AUTHOR]

This paper presents the potential of Ultra-High Definition TV (UD-TV) broadcasting transmission systems beyond HD-TV over cable channels. Firstly, we analyzed the trend of the TOV (Threshold of Visibility) by extending the OpenCable (J.83 Annex B) system, 256QAM, which is the standard for American and Korean cable television transmission to 1024QAM, and found that the latter has a nearly 30% higher data rate than the former at the expense of an impractically high TOV. To achieve a practical TOV, we vary the code rates of the inner convolutional coder and replace the turbo codes in the forward error correction (FEC) part, thereby analyzing the best performance of the OpenCable systems using conventional FEC. The results showed that, it is necessary to modify the conventional FEC of the OpenCable system to achieve a TOV less that 31.5dB. Moreover, we study the potential of UD-TV transmission via two or more TV channels, which is known as channel bonding, by examining the Shannon capacity in a 6MHz channel and the relationship with next generation A/V codec technologies. [ABSTRACT FROM AUTHOR]

The resolution of the latest digital display systems, such as high-definition television (HDTV), has increased, making its visual quality a key selling point in the current consumer electronics market. Color transient improvement (CTI) is the process used to reduce the color edge transition time, so that current market demand for the high quality visuals in digital display systems can be achieved. In this paper, we present a CTI method with transient detection and variable length nonlinear filtering that enhances the color edge characteristic of a digital color display system, such as HDTV. The proposed method is based on a transient detection-based CTI algorithm and a variable length nonlinear filtering algorithm. Experimental results show that the proposed method effectively improves the color transient and also solves the problem of the shoots occurring during the CTI process. [ABSTRACT FROM AUTHOR]

The next frontier for High-Definition Television is stereoscopic displays that enhance the viewing experience. This paper proposes an innovative method of creating a high- quality stereoscopic display utilizing a Spatial Light Modulator called a Digital Micro-mirror Device and high-contrast shutter glasses. [ABSTRACT FROM AUTHOR]

In this paper, a novel pipelined intra prediction scheme with prediction mode scheduling is proposed to design H.264/A VC video encoder for high-definition TV (HDTV) applications such as ND camcorder. Since the intra prediction of the current 4×4 block cannot be performed before the reconstruction of a previous 4×4 block, intra 4×4 prediction cannot be pipdined for high speed implementation. By rearranging the encoding order of intra 4×4 prediction, the proposed scheme can be pipelined while maintaining consistency with the standard. In order to further increase the hardware utilization, the prediction order of the nine intra 4×4 prediction modes is scheduled depending on the required pixels to generate the predicted images. With the proposed scheme, the intra 4×4 prediction can be pipelined, and the bubble between the blocks can be decreased without the performance degradation. Since the processing time is reduced by up to 41%, it can save the hardware resource. Thus, the proposed scheme can be a good solution for real-time ND sized encoding applications. [ABSTRACT FROM AUTHOR]

A new motion compensated deinterlacing method using forward and backward motion estimation is proposed in this paper. Bi-directional motion estimation is performed using two previous and two subsequent fields. The motion estimator uses pre-filtering prior to motion estimation for the current and the subsequent two fields. The motion estimator finds a single optimal matching block in the same or opposite parity reference fields. Motion compensation is done according to the amount of vertical motion within the reference fields to achieve the highest vertical resolution improvement. A novel technique to prevent the appearance of visual artifacts in the presence of fast-moving objects is proposed. Experimental results show that the proposed method performs better than the conventional deinterlacing methods, based on objective and subjective criteria. [ABSTRACT FROM AUTHOR]

Plasma display panel technology employs a pulse-number modulation method to generate the gradation of the display. However, this method can create a false contour distortion when moving pictures are reproduced. In this paper, we propose an effective subfield optimization technique which is based on measuring motion picture distortion. To this end, we propose two applications of the measurements. One is optimum selection of the codewords to improve performance, and the other is the application of rough sets theory to subfield optimization, which reduces computational CPU time. Simulation results show that dynamic false contouring can be effectively reduced by this optimization technique, and the complexity can be minimized using rough sets theory. [ABSTRACT FROM AUTHOR]

In the encoder of the national television system committee (NTSC) system, a composite video burst signal (CVBS) is generated using the luminance (Y) signal and the quadrature amplitude modulation (QAM) modulated chrominance (C) signal. In the decoder, it is important that the CVBS be accurately separated into luminance and chrominance signals by a Y/C separation filter. Otherwise, various artifacts, such as dot crawl, rainbow effect, and color bleeding, appear in a decoded video, degrading the quality of the decoded video. In addition, modern high-definition television (HDTV) system suffers from outdated analog decoding artifacts when HDTV compression techniques were applied to the not ideally decoded former standard-definition format video images. This paper proposes artifact reduction methods of dot crawl and rainbow effect using the characteristics of the CVBS video. The proposed artifact reduction algorithms use two successive frames, in which the decoded video images are divided into not moving (stationary) and moving regions. The stationary regions are filtered by a temporal filter whereas the moving regions are further classified into three subdivided regions of different types of artifacts to apply them into temporal or spatial filters because inappropriately temporally filtered moving region delivers jitters on the edge. In the proposed algorithms, considering characteristics of the NTSC decoded image, a block matching algorithm based on 4×4 non-overlapping blocks is used for motion estimation and compensation. Computer simulations with various simulated and real videos containing NTSC artifacts show the effectiveness of the proposed artifact reduction methods. [ABSTRACT FROM AUTHOR]

A new single chip HDTV H.264 codec system LSJ was designed using flexible codec architecture. It supports HP@L4.1 with full 1920x1080 resolution. The LSI supports MPEG2 and JPEG as well. The chip integrates one encoder and two decoders, which work independently and can be used in flexible ways including transcoding. It also integrates almost all the necessary functions for digital consumer application including an audio codec, graphics and video circuitry, peripherals, and a generic microprocessor. [ABSTRACT FROM AUTHOR]

In this paper the authors describe a clock synchronization system with buffer management mechanism that enables "TV adoptable quality" of HD (High Definition) video transmission via wireless network Like DLNA (Digital Living Network Alliance), the usage of IP based network for CE devices, especially for Audio Video appliance, is increasing its importance. Compared with IT technology based devices such as a PC, consumers expect CE devices to provide more stable functions and higher quality. CE devices are expected to provide Audio Visual contents including HD video contents with the quality better than that can be achieved with Internet streaming on a PC. . Based on well considered simulation for wireless network usage at home, we have developed the buffering system with its optimized size that can offer high quality HD video transmission service to CE oriented customers. [ABSTRACT FROM AUTHOR]

A new system for selectively displaying fighting scenes of Sumo matches on a live HDTV video stream was built for the mobile phone set. The specific scenes of the Sumo matches were picked up, enlarged, and displayed in real-time on the QVGA display of a mobile phone set. The decision on the start fighting on the Sumo match scene was made by the Mahalanobis distance method applied to the number of the motion vectors toward left or right in each of the respective blocks on a frame. The decision on the end of Sumo match scene was made by the total motion vector magnitudes on the "end of Sumo match" frame. [ABSTRACT FROM AUTHOR]

In this paper, we propose an optimized real- time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with NW/SW partitioning. A VS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32- bit RISC processor. We further propose the optimization of Interface and RISC processor based on the proposed architecture. The A VS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip A VS HDTV real-time decoder. At 148.5MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board. [ABSTRACT FROM AUTHOR]

In this paper, we present a VLSI design of transport processor for an A VS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bus architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18μm CMOS cell library. The circuit costs about 75k equivalent logic gates and the processing capability is up to 90Mbps. [ABSTRACT FROM AUTHOR]

The design effort of software system in Multi-processor System-on-a-Chip (MPSoC) is getting heavier with ever-increasing system complexity. The design methodology mainly focuses on things such as co-development with hardware, reducing cost and time, and increasing portability, reusability, and robustness. This paper explores how to design a high performance, robust software system with component-based method and systematic level co-development. Complex architecture and system requirements constrain the whole process. High Definition Television (HDTV) decoder SoC platform consists of two processors and customized hardware and software components. As an successful experience, we will give the software component design and implementation details. [ABSTRACT FROM AUTHOR]

Rich requirements from High Definition Television (HDTV) decoder argue the supports of complex architecture and Operating System (OS). As an embedded system, mult-processor System-on-a-Chip (MPSoC) is an ideal implementation of the decoder. Open source OS has many advantages to be ported to embedded fields. This paper describes the detailed process of its porting, including building environment, kernel modification, and debug. The porting specifications are constrained by the resources on the HDTV SoC platform, development period, debug efforts, and system robustness, etc. As an application of the open source OS, our work shows the joint of industry practice and theory research. [ABSTRACT FROM AUTHOR]

In this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-Golomb Code, and AVS 2-D Variable Length Code. Furthermore, it has a pre- processing submodule, which can perform Start Code Detection and De-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18µm Artisan CMOS cells library by Synopsys Design Compiler. The circuit costs about 15k equivalent logic gates (not including 4kb on-chip SRAM). And the critical path is less than 6ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards. [ABSTRACT FROM AUTHOR]

The reception of high-definition television in a mobile environment with the same quality as that achieved at home has been considered to be difficult to achieve. In an attempt to solve this problem, we have developed an adaptive beam steering reception system and evaluated the performance of this new system by both indoor and outdoor experiments involving the reception of high-definition television. The experimental results revealed that the reception performance was significantly improved, such that terrestrial digital television broadcasts can be received in high-speed moving environments, and with the same stability as broadcasts that are received at home in a fixed reception area. [ABSTRACT FROM AUTHOR]

We propose a residential HDTV distribution system that is composed of UWB and IEEE 1394. This system converts multi-channel MPEG TS broadcasting data into IEEE 1394 packets or UWB packets based on IEEE802.15.3 WPAN. Any distributed UWB packets are again converted into MPEG TS data through a UWB-to-IEEE1394 bridge. Moreover, this system can also transmit IPTV packets encapsulated with IEEE 1394 packets from a home gateway or home server to a home UWB network. We implement UWB MAC and physical layer chips using CMOS ASICs. [ABSTRACT FROM AUTHOR]

This paper presents a home server platform integrating the functions of communication, digital broadcasting reception, and home automation applications. The home server has a processing module of high performance to process software task, and a multimedia decoding module as a peripheral component interconnect slave device to decode the audio and the vide data compressed in various formats, and a home automation module to provide home control services, and a MPEG2 transport stream (TS) distributor to convey simultaneously three high definition television (HDTV) channels which may go their way from terrestrial, satellite, and cable tuners to the next destination via home network. For an implementation of this integrated home sever we have had to manipulate the video and audio paths from processing module, home automation module and tuner modules to display the selected one on HDTV set. In order to convey Internet protocol television (IPTV) traffic through this integrated home server a QoS-enabled Ethernet switch is mounted to the processing module. [ABSTRACT FROM AUTHOR]

This paper proposes an image display processing system that reduces the core performance of the processor allocated in the image display, thereby enabling the use of a less expensive low-performance processor. Essentially, the proposed system supports a high-resolution image display function in an electronic picture frame (EPF) module using a low-performance processor based on converting HD image data at a 15Hz frame rate into HD image data at a 60Hz frame rate for use in a digital TV system. As a result, the proposed system can reduce the processor performance to a level corresponding to an image display with a low frame rate, thereby reducing the product cost and allowing various additional functions. Finally, the proposed system is implemented to confirm its effectiveness. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new post-processing method, based on the theory of the projection onto convex sets (POCS) to reduce the blocking artifacts in digital high definition television (HDTV) decoded images. We propose a new smoothness constraint set (SCS) and its projection operator in the wavelet transform (WT) domain to remove unnecessary high-frequency components caused by blocking artifacts. We also propose a new method to find and preserve the original high frequency components of the image edge. Experimental results show that the proposed method can not only achieve a significantly enhanced subjective quality, but also exhibit the PSNR improvement in the output image. [ABSTRACT FROM AUTHOR]

A new overlap-scan circuit that enables a high speed scan or low data voltage scan based on overlapping the scan pulses during a scan-period is proposed for a 42-in. plasma TV. For the overlap between the scan pulses, the proposed overlap-scan circuit consists of three odd and three even drivers that alternately provide the scan pulses to the odd and even scan lines among the 480 scan lines, respectively. Consequently, the proposed overlap-scan circuit can perform either a high-speed scan by reducing the total scan time or a low voltage scan by lowering the address voltage. [ABSTRACT FROM AUTHOR]

In this paper, we proposed a parallel and pipeline architecture for the sub-pixel interpolation filter in H.264/AVC conformed HDTV decoder. To efficiently use the bus bandwidth, we bring forward three memory access optimization strategies to avoid redundant data transfer and improve data bus utilization. To improve the processing throughput, we use parallel and multi-stage pipeline architecture for conducting data transmission and interpolation filtering in parallel. Moreover, To balance the tradeoff between memory accessing scheme and sub-pixel interpolation processing granularity we devise a dedicated buffer organization to convert free-structured block size reading to fixable and sequential processing. As compared to the traditional designs, our scheme offers 60% reduced memory data transfer. While clocking at 66MHz, our design can support 1280x720@30Hz processing throughput The proposed design is suitable for low cost and real-time applications. Moreover, it can easily be applied in system-on-chip design. [ABSTRACT FROM AUTHOR]

In TDS-OFDM (Time-Domain Synchronous Orthogonal Frequency Division Multiplexing) systems, pseudonoise (PN) sequences rather than cyclic prefixes are inserted as guard interval, between consecutive inverse discrete Fourier transformed (IDFT) symbol blocks. Since the PN sequences can also be used as training symbols, such system can provide higher spectrum efficiency. However, due to non-cyclic property of the signal, the simple channel estimation and equalization techniques for conventional cyclic prefixed OFDM (CP-OFDM) can not be applied to TDS-OFDM in this paper, we propose a channel estimation and equalization method for TDS-OFDM. Channel estimation depends on time domain correlation and iterative interference cancellation techniques, while equalization is based on tail cancellation and cyclic restoration algorithm (TCCR). It is shown that our proposed method can provide satisfactory performance in TDS-OFDM based terrestrial high-definition television (HDTV) broadcasting system. [ABSTRACT FROM AUTHOR]

A novel architecture of transport stream demultiplexer (TS Demux) in high definition television (HDTV) decoder is presented in this paper, which utilizes a cooperation scheme between hardware and software. TS parsing is decomposed into two phases: filtering and analyzing, which are fulfilled by hardware and software respectively. Meanwhile, the hardware filtering is con trolled by the software. Two filtering layers, PID and Section filtering, are supported by hardware, which can extract any format data in TS stream quickly. Compared to the current parsing scheme for TS packets, TS Demux discussed here needs less CPU resource and is easy to update as well'. [ABSTRACT FROM AUTHOR]

In this paper, an efficient decision feedback equalizer (DFE) is presented for sparse channels with large delay echoes, which are encountered in many high-speed wireless communication applications. Unlike the conventional DFE, this proposed equalizer considers that the channel is sparse and large number of DFE taps lead to noise accumulation problem. The new method can achieve efficient equalization by setting the active group for equalization taps and clearing the abandoned taps mechanism. As a result, it can both reduce hardware implementation complexity effectively and improve the performance compared to the conventional DFE. Brief analysis about noise accumulation effects in large-scale equalizer and working mechanism description of this effective algorithm exhibits us where the performance gain lies. Simulation results show that this modified DFE exhibits considerable computational savings, faster convergence, and better performance and improved tracking capabilities than the conventional ones. It is quite fit for applications in high-speed systems, such as high definition television (HDTV) and broadband mobile communication. [ABSTRACT FROM AUTHOR]

We have proposed novel pixel circuits and driving methods for a-Si TFT-LCDs that can reduce the numbers of both column and row lines to half of those of traditional a-Si TFT-LCDs for a given resolution format Whereas one pixel of a traditional TFT-LCD is driven by a row line and a column line connected to the gate and the source of the thin film transistor respectively, the proposed novel TFT-LCD allows neighboring four pixels to share a gate line and a data line, thereby reducing the numbers of both column and row lines to half This leads to halving the numbers of the row and the column driver ICs, cutting down the cost of the driver IC to half For the full-spec. HDTV (1920×3×1080), traditional TFT-LCDs need 12 column driver ICs with 480 outputs and 4 row drivers with 270 outputs. The proposed column-and-row-line sharing method allows the same TFT-LCD to be driven by 6 column driver ICs with 480 outputs and 2 row drivers with 270 outputs, halving the cost of the driver IC. [ABSTRACT FROM AUTHOR]

Channel variation during an OFDM block leads to the loss of orthogonality among subcarriers, resulting in inter-carrier interference (ICI) in orthogonal frequency division multiplexing (OFDM) systems. Many schemes have been proposed to suppress ICL but they are computationally complex or at the price of sacrificing bandwidth. In some cases, such as high-density television (HDTV) broadcasting and satellite OFDM systems, the very long delay spreads pose the possibility that the channel length exceeds that of the moderate cyclic prefix (CP), resulting in intersymbol interference (ISI) and intercarrier interference (WI). A time- domain equalizer (TEQ) is usually used in the receiver to reduce the duration of the overall response of the transmission system, and therefore minimize the ISI and ICI However, the optimum design of TEQ turns out to be a difficult task The ICI's introduced by insufficient CP and channels variations are different and usually exploit different methods to mitigate them. In this paper, we provide an ICI and ISI analysis in time- and frequency- domain for OFDM systems with insufficient CP over time-variant channels. Basing on this analysis, we propose an iterative method for joint ICI and ISI cancellation whose complexity is linear in the OFDM symbol length. Theoretical analysis and simulation results indicate that the proposed method can effectively mitigate ICI and ISI introduced by channel variation and insufficient CP with high bandwidth efficiency. [ABSTRACT FROM AUTHOR]

Timing jitter, frequency offset, carrier phase jitter and sampling clock frequency offset are the main synchronization errors encountered by OFDM systems. As many literatures have proved, OFDM systems are very sensitive to frequency errors. In this paper, three new methods to estimate the integer part of frequency offset are proposed, simulation results show its robustness to mitigate the multi-path effect and its enlarged estimation range for frequency offset The correspondent Field Programmable Gate Array (FPGA) circuit through test in HDTV prototype in Team of Engineering Expert Group (TEEG) proves its feasibility and availability. The proposed method is also suitable for burst mode transmission systems such as Wireless Local Area Network (WLAN) and Fixed-Broadband Wireless Access (F-B WA). [ABSTRACT FROM AUTHOR]

Insufficient pixel charging time has come up as one of the most serious problems, as the resolution format of TFT-LCDs grows higher and the display area gets larger. In order to resolve the problem, we have proposed a new driving scheme coined LiTEX (Line lime Extension) that can actually extend the available row line time for adequate pixel charging. This approach based on the driving method is very desirable, because we can achieve higher resolution formats or larger display, even if the same process technology is given. The simulation results show that 40-inch a-Si TFT-LCDs for full-spec. HDTV (1920×1080) can be achieved using the proposed driving method [ABSTRACT FROM AUTHOR]

This paper presents advanced rate control technologies for 3D-HDTV. We remodel the quadratic rate- distortion model for 3D multiview sequences based on their picture types. The proposed method consists of two levels for more accurate bits rate control In a frame level, it sets quantization parameters based on HVS (Human Visual System) and reduces error bits by remodeling rate-quantization. In a MB level, rate control is activated to provide stricter buffer regulations and higher bit rate encoding based on the target bits and the quantization parameters calculated at the frame level. The proposed algorithm shows improvements in rate control as well as in PSNR compared to the conventional methods. It also provides more accurate rate control and higher image quality than TM5 and TMN8 at various bits rates. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new deinterlacing algorithm which is an edge dependent interpolation (EDI) algorithm based on a horizontal edge pattern. Generally, a conventional EDI algorithm has a visually better performance than any other deinterlacing algorithms using one field However, it produces unpleasant results due to the failure of estimating edge direction. In order to exactly detect edge direction, we use not only simple difference but also edge patterns. Experimental results indicate that the proposed algorithm outperforms conventional approaches with respect to both objective and subjective criteria. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel postprocessing technique based on the theory of the projection onto convex sets (POCS) in order to reduce the blocking artifacts in digital high definition television (HDTV) images. By detecting and eliminating the undesired high-frequency components, mainly caused by blocking artifacts, we propose a new smoothness constraint set (SCS) and its projection operator in the DCT domain. In addition, we propose an improved quantization constraint set (QCS) using the correlation of DCT coefficients between adjacent blocks. In the proposed technique, the range of the QCS is efficiently reduced as close to the original DCT coefficient as possible to yield better performance of the projection onto the QCS. Computer simulation results indicate that the proposed schemes perform better than conventional algorithms. Furthermore, we introduce a fast implementation method of the proposed algorithm. The conventional POCS-based postprocessing techniques require the forward/inverse discrete cosine transform (DCT/IDCT) operations with a heavy computational burden. To reduce the computational complexity we introduce a fast implementation method of the proposed algorithm that does not perform DCT/IDCT operations. Estimates of computation savings vary between 41% and 64% depending on the task. [ABSTRACT FROM AUTHOR]

To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. In a HDTV decoder system, experimental results show that the proposed scheme reduces the memory latency and the energy consumption by 18.8% and 23.3%, respectively, over the conventional scheme that always keeps the memory in idle state. A hardware architecture and its VLSI implementation are also presented. [ABSTRACT FROM AUTHOR]

Motion-JPEG2000 (1S015444-3, [1]) is a new intraframe-based video compression standard, which preserves best image quality after compression for use in high quality video systems like HDTV-cameras, medical imaging cameras or Digital Cinema cameras. This paper describes the advantages of the new standard in comparison to other standards, lists typical applications for the new standard and points out implementation challenges for electronics in real- time systems. A comparison of Motion-JPEG2000 with MPEG-2 is presented and realization concepts with combined hardware/software solutions like FPGA and embedded microcontrollers are shown. The scalability of video in the new standard provides new opportunities for efficient postproduction and distribution channels in the video processing chain.[SUP1] [ABSTRACT FROM AUTHOR]

Focuses on a study that presented a rewritable optical disk with a capacity of 30GB/side intended for the next generation of rewritable optical disks for high definition television. Demand for the next optical disk; Key technologies; Experimental results; Conclusion.

Suggests an implementation procedure and a novel bit-allocation strategy for a digital High Definition Television (HDTV) encoder system with parallel processing architecture based on six horizontal strips division. Capability of Multiple Sub-pictures Encoding Modules in performing MPEG-2 coding; Deduction of the joint bit-allocation strategy for sub-pictures encoding and the auxiliary rate adaptive procedure for scene changes; HDTV video encoder implementation.

Describes timing and synchronization considerations in the development of the third generation high-definition television encoder in China. Design of timing stamps; Characteristics of the timing and synchronization system; Experimental result.

Proposes an improved multimedia database system consisting of an image server, a directory server and user terminals which are connected together through the Japan Gigabit Networks. Function of the image server; Function of the image directory; Appearance of the high-definition image on the high-definition television display.