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Variable block-size motion estimation (VBSME) has become an important technique in H.264/A VC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/A VC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an "as-early-as-possible" basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 μm standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF). [ABSTRACT FROM AUTHOR]

This paper presents an HDTV video decoder core that is able to decode MPEG-2, MPEG-4 A VC and VC-I formats and is fully compatible with the Blu-ray Disc standard. The core has two major features which achieve low-cost hardware implementation for three different standards. First, a novel re-configurable architecture is adopted to realize reduced hardware for three different variable length coding tables. A hybrid architecture that consists of a cell array and coefficients memory is introduced By considering the trade-off between performance and cost, the cell array can compare a variable number of bits in a flexible manner. Second, a data compression method suitable for all video decoding standards is applied to reduce memory data usage and access bandwidth. A compression syntax based on Run-Level encoding with Exp-Golomb tables is used to achieve both low compression workload and reasonable memory cost. The core is implemented by top-down HDL basis approach, and the circuit volume is 1.5Mgates with 9Onm CMOS technology and operation clock.frequency is 162MHz for 1080i at 30fr/s. [ABSTRACT FROM AUTHOR]

To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4.4:4 1920 × 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features. [ABSTRACT FROM AUTHOR]

Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264 and the Chinese AVS, many efficient coding tools have been introduced into MC, such as new motion vector prediction, bi-directional matching, quarter precision interpolation, etc. However, these new features enormously in crease the computational complexity and the memory bandwidth consumption. In this paper, we introduce a novel architecture design of Motion compensation (MC) for multiple video standards including MPEG-2, H.264, and AVS. The proposed design has a macroblock-level pipelined structure which consists of MV Predictor, Cache- based Fetch, and Pixel Interpolation unit. The proposed architecture exploits the parallelism in MC algorithm to accelerate the processing speed and uses the dedicated design to optimize the memory access. MV Predictor unit can cover all MV prediction algorithms for the three standards and provide a simple error concealment scheme. Cache-based Fetch unit can save 25% memory, bandwidth of MC in average and doesn't impact the performance in the worst case. Pixel Interpolation unit adopts fully separate 1-D filtering structure which is designed to effectively avoid the redundant calculations. The architecture can achieve the real-time multiple-standard decoding for HDTV 1080i (1920×1088 4:2:0 6Ofield/s) video. The efficient design can work at the frequency of 148.5MHz and the total gate count for logic circuits is about 56K. [ABSTRACT FROM AUTHOR]

Motion estimation (ME) is the most critical component of a video coding system, and it also dominates the major part of computation complexity and memory bandwidth. For H.264/AVC integer motion estimation (IME,), this paper presents a novel memory-access and computation efficient full-search block-matching hardware architecture. With the highest level of on-chip data reuse, one-access for off-chip reference pixels is achieved, and the off-chip memory bandwidth is thus minimized. By distributed data caching and virtual connection of reference picture boundaries, the data traffic scheduling is simple, regular and efficient. The computation engine employs a two-dimensional (2-D) systolic processor array to calculate the absolute differences in single-instruction multiple-data (SIMD,) manner, and 2-D adder trees to sum up the absolute differences, all with 100% utilization. The proposed architecture fully supports variable block-size matching of H.264/AVC, and can produce 41 sums of absolute differences (SADs.) for one search point every cycle without bubble. The architecture is described in parameterized design, and an implementation for standard- definition digital TV encoding applications is presented. Theoretical analysis and experimental results show that, the proposed architecture can achieve the minimum off-chip memory bandwidth and the maximum computational performance. [ABSTRACT FROM AUTHOR]

This paper presents a full search motion estimation algorithm with search center prediction for A VS and the VLSI architecture to realize the algorithm. The proposed algorithm achieves comparable performance in coding efficiency with the anchor algorithm, whereas has low storage requirement, low required bandwidth and low complexity for the hardware implementation. The proposed architecture adopts J-D FE Arrays architecture and can perform variable block size motion estimation with 70k logic gates and 24kbits on-chip memory. The architecture achieves best tradeoff in terms of speed and hardware cost. The design can satisfy real-time encoding for A VS high definition application of 1280x720 picture size at 60 fps. [ABSTRACT FROM AUTHOR]

This paper proposes a novel flexible VLSI architecture for the implementation of variable block size motion estimation (VBSME). The architecture is able to perform a full motion search on integral multiples of 4 × 4 blocks sizes. To use the architecture, each 16×16 macroblock of the source frames should be partitioned into sixteen 4 × 4 non-overlapping subblocks, called primitive subblocks. The architecture contains sixteen modules and one VBSME processor. Each module, realized by cascading ID systolic arrays, is responsible for the block-matching operations of a different primitive subblock. The realization has the advantages of high throughput, high flexibility and 100 % processing element (PE) utilization. The motion estimation of all the primitive subblocks are performed in parallel. Because these primitive subblocks can be used to form the 41 subblocks of different sizes specified by the H.264, the VBSME processor is employed to concurrently compute the sums of absolute differences (SADs) of all the 41 subblocks from the SADs of the primitive subblocks. This new architecture has lower latency and higher throughput over other exiting VBSME architectures for the hardware implementation of H.264 encoders. [ABSTRACT FROM AUTHOR]

This paper presents an efficient VLSI architecture of the (248, 216) Reed-Solomon decoder with erasure correction capability for Bitt-ray Disc (BD). The proposed architecture is designed with four-stage pipelines: the syndrome and erasure location polynomials calculation, the errata location polynomial calculation, the errata evaluation polynomial calculation, and the Chien search and errata value evaluation. Each stage is carefully balanced to maximize the throughput of the pipeline for BD applications. To solve the key equation, the Berlekamp-Massey algorithm is transformed into a symbol-serial structure and the fully utilized VLSI architecture, maintaining the maximum decoding performance, is proposed. Therefore, the proposed architecture maximizes the throughputs requiring less hardware resources. The gate counts for the proposed RS decoder is 74K using the Hynix 0.35um standard cell library and the maximum throughput is 700Mbpsc@4100MHz, which is fast enough for 16x BD applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a generic bit-sliced rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank- order filtering, threshold decomposition and polarization. In conventional designs, these operations are usually implemented as logic circuit and require complex computation. Using the memory-oriented architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed PMM has features of bit-sliced read, partial write, and pipelined processing. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits for parallel read/write operations. Combining the bit-sliced read with polarization selector allows PMM to perform polar determination while the partial write achieves polarization. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed. [ABSTRACT FROM AUTHOR]

The Motion estimator is a key element in many video compression systems and it tends to dominate the power consumption in them. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is essential. To meet this requirement, this paper presents a novel power-aware architecture, called the Vario-Power Architecture, for the motion estimation. Based on a semi- systolic array with the content-based subsample algorithm, the architecture real-time disables some processing elements to reduce power consumption. By performing the edge extraction first, a threshold is then set as the criterion of whether to enable or disable processing elements and thus the switch activities of the system can be reduced As the simulation shows, the architecture may operate at different power consumption modes according to the remaining capacity of the battery pack giving little quality degradation and the power overhead under 0.36%. [ABSTRACT FROM AUTHOR]

This paper presents a flexible qualityadjustable H.264 intra frame encoder for power aware video applications. Encapsulating a reconfigurable algorithm, the proposed design can configure the encoding search algorithm to operate at different quality modes with the design tradeoff between video quality and power consumption. In addition, some timing optimization schemes are proposed to increase the hardware throughput of the proposed design to encode H.264 intra video sequences on D1, HD720 and HD1080 with 10 mW to 16 mW, 27 mW to 45 mW, and 60 mW power consumption under different quality modes, respectively. Implemented by using a 90nm CMOS technology, the proposed design comprises 91 kgates and 2.9 kB internal memory. [ABSTRACT FROM AUTHOR]