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We derive analytically expressions for the probability distribution of the propagation delay time of logic signals through a CMOS inverter when the inverter power supply voltage $V_{{\text{dd}}}$ (more precisely, gate voltage $V_{{\text{GS}}}$) is itself probabilistic for some reason (e.g., system noise or a random external electromagnetic disturbance). Since the propagation delay time is a function of the value of $V_{{\text{dd}}}$ , then some values of $V_{{\text{dd}}}$ may produce values of the inverter propagation delay time that cause the circuit in which the inverter resides to malfunction (e.g., by resulting in an inverter delay time value not conforming with the delay time margins for that circuit). Based upon the derived inverter propagation delay time probability distribution, we then derive a probability for the malfunction of a circuit containing a single inverter subject to such a stochastic $V_{{\text{dd}}}$. In this paper, we present no discussion of the application of our formalism to example probability density functions for $V_{{\text{dd}}}$ ; we rectify this situation by presenting three detailed such examples in a companion paper in this journal. [ABSTRACT FROM AUTHOR]

In a variable speed drive (VSD) system, high-frequency switching of power devices will cause large common-mode (CM) voltage during operation. While the CM voltage acts on the parasitic capacitance of the system, it will generate serious CM current on the motor side. It is necessary to model the VSD system so as to analyze and forecast the CM current theoretically. However, an essential condition of modeling CM current is to extract the CM impedance on the motor side of the system. In this paper, a novel extraction method for the CM impedance of an inverter-fed induction motor is proposed. First of all, time-domain waveforms of the CM voltage and current on the motor side of the VSD system are measured, and then mathematical calculations are performed to obtain the spectrum characteristics of the CM impedance on the motor side of the system. Compared to the traditional extraction methods of the impedance parameter by an impedance measurement or numerical calculation, the method proposed in this paper does not require laborious modeling of the motor or cable, and the extraction process is much simpler and easier. Moreover, in traditional methods, the motor impedance parameters are usually obtained in a nonworking state, while the proposed extraction method can be conducted in working state. Thus, the CM impedance extracted by the proposed method will be more accurate. Through comparing measurement and the simulation results of the CM current on motor side, the proposed CM impedance extraction method for an inverter-fed induction motor is validated. [ABSTRACT FROM PUBLISHER]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. The function can be easily obtained and used in jitter budget calculation. [ABSTRACT FROM PUBLISHER]

In a power inverter configuration with pull-up and pull-down transistors, ringing that occurs on the high-to-low and low-to-high transitions can be used to track aging or degradation of the transistors and potentially predict failures. Changes in a transistor's equivalent resistance and capacitance can affect the frequency and damping factor of the characteristic ringing detected on the inverter's output. In this paper, the matrix pencil method is used to locate the poles associated with this ringing, and detect shifts in position that indicate transistor degradation. [ABSTRACT FROM AUTHOR]

The aim of this paper is to describe a first- approximation model that predicts the emissions radiated by an induction-machine motor drive. The proposed model can be used in the design stage of an asynchronous motor drive. A three-phase induction machine supplied by a voltage-source inverter is studied; both square-wave and pulsewidth modulations of the power converter are considered. Computer simulations are presented to prove the validity of the proposed model. The applications considered lead to numerical results that are in qualitative agreement with those calculated and/or measured by other authors. [ABSTRACT FROM AUTHOR]

This contribution deals with the optimal placement of the decoupling capacitances on the gridded power delivery network of a multichip assembly with interposer. The optimization is performed by means of a nature-inspired algorithm of the genetic class. Different placement strategies are considered and compared. The cost function is based on the evaluation of the input impedance looked into the power and ground rails of the power distribution network and its comparison with a user-defined mask. [ABSTRACT FROM AUTHOR]

This correspondence discusses the implementation of clock slope control to reduce emissions from fully-integrated step-up dc/dc converters. The addition of clock slope control is a common technique used to reduce electromagnetic emissions normally associated with charge pumps. The clock slope control is coupled with frequency and current control voltage regulation methods. [ABSTRACT FROM AUTHOR]

The effects of electromagnetic interference (EMI) from high-power microwave signals on the operational integrity of CMOS inverters are reported. The static characteristics of inverters were measured with and without the injection of microwave signals at power levels of up to 24 dBm and frequencies between 800 MHz and 3 GHz. Voltage transfer characteristics showed significant changes in output voltages, and substantial reduction in gain with microwave interference, due to increased drain currents and reduced transconductance, respectively. The asymmetry of the MOS devices (size, mobility) designed to provide balanced current driving capability, results in significantly imbalanced current driving capabilities under interference. A substantial increase in the static power dissipation at the stand-by "ON" and/or "OFF" states, is observed. Degradation in the noise margins and severely com- pressed input/output voltage ranges were observed due to large changes in voltage characteristics, invalidating noise immunity of cascaded CMOS inverters, and leading to serious bit-flip errors. The load-line characteristics showed substantial shift in the quiescent point of operation, and changes in the effective "ON" resistance of the MOS devices, resulting in increased current in the inverters. The input/output voltage range-related bit-flip errors and the static power dissipation problems, represent the most critical vulnerabilities in the operational integrity of digital systems. [ABSTRACT FROM AUTHOR]