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Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

In this paper, we study the effect of highly doped n^+/p^+ Si as the bottom electrode on unipolar RRAM with Ni-electrode/\HfOx structure. With heavily doped p^+-Si as the bottom electrode, RRAM devices illustrate the coexistence of the bipolar and the unipolar resistive switching. Meanwhile, by substituting heavily doped n^+-Si, the switching behavior changes to that of the self-rectifying unipolar device. The asymmetry and rectifying reproducible behavior in a n^+-\Si/HfOx/\Ni device resulted from the Schottky barrier of defect states in the \SiOx/\HfOx junction and n^+ Si substrate, but this behavior is not seen for the p^+-Si bottom electrode case. With rectifying characteristics and high forward current density observed in the \Ni/HfOx/\n^{+}\Si device, the sneak current path in the conventional crossbar architecture was significantly suppressed. We believe that the proposed structure is a promising candidate for future crossbar-type RRAM applications. [ABSTRACT FROM AUTHOR]