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In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

All resistive switching memory devices face a critical voltage-time dilemma, as they require fast write at moderate voltage together with disturb immunity at lower (read) voltage. In this paper, excellent voltage-time characteristics are demonstrated on a 90-nm CMOS-friendly W/Al2O3/TiW/Cu conductive-bridging memory cell. The switching voltage was evaluated in the large write pulsewidth range between 10 ns and 10 s, from which a very low slope of $\sim 75$ mV/decade was extracted. These characteristics allow, on the one hand, a fast switching (10 ns) at <3 V, and, on the other hand, excellent voltage-disturb immunity extrapolated to ±0.5 V for 10 years. Both constant-voltage-stress and read-endurance tests supported these predictions. By means of conductive-atomic-force microscopy tomography, the hourglass shape of the Cu filament was evidenced. Both the more distributed electrical field induced by this shape along the filament and the analysis of a charge-transfer (redox) reaction as rate-limiting mechanism in the switching process are discussed as the origins of this excellent disturb immunity. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

We demonstrate the ink-jet printed fabrication technique for TiO2-based memristor, followed by detailed analysis of electrical characteristics and development of a new model that considers observed phenomena of quantized conductance steps. The existence of pinched hysteretic current–voltage characteristics is evidence of memristive behavior, provided by the reversible atomic rearrangement taking place in the functional layer. For the first time, performed electrical measurement on the micrometer thickness devices based on TiO2 active layer has captured the plateaux steps of the conductance at integer multiples of elementary quantum conductance. This behavior is consistent with the assumption that transport from electrode to electrode emerges through confined paths of conductive filaments with radius in the nanometer size range. Moreover, we introduce a novel model, based on the diffusion equation for ballistic transport in memristive devices, which considers the conductance plateaux steps. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

The amorphous phase of the chalcogenide material in phase-change memory (PCM) devices is sensitive to temperature-activated crystallization and structural relaxation (SR). The latter leads to a change of device/material properties, such as the mobility band gap, the resistance, and the threshold voltage VT for threshold switching. In this paper, we present a VT drift model based on physical descriptions of the electrical transport, the threshold switching, and the SR. We introduce an analytical formula describing the relation between the drift slopes of resistance and VT via the subthreshold slope STS of the I– V curve. A numerical model predicting the time evolution of VT for different programmed states in the PCM multilevel cell is finally presented and compared with experiments. [ABSTRACT FROM PUBLISHER]

Physics-based compact models for redox-based resistive switching memory (ReRAM) devices are used to increase the physical understanding of the complex switching process as well as to allow for accurate circuit simulations. This includes that models have to cover devices showing bipolar switching (BS) and complementary switching (CS). In contrast to BS devices, which store the information in (at least) one high and one low resistance state, CS devices use (at least) two high resistance states. Applications of CS devices range from passive crossbar arrays to novel logic-in-memory concepts. The coexistence of CS and BS modes in one device has been shown experimentally. Here, a physics-based compact model describing BS and CS consistently is presented. Besides modeling CS devices, the model improves the description of BS as it allows to reproduce and explain anomalies in the BS RESET process. The model includes ion drift and diffusion along the filament. The influence of different parameters on the drift–diffusion balance is discussed. [ABSTRACT FROM AUTHOR]

Filamentary conduction paths through insulating solid electrolytes is a widely accepted theory describing the conductionphenomenon in resistive random access memories (RRAMs). In this work, the relationship between filamentary conduction and multilevel resistive states obtained as a result of V\text {STOP} during the RESET process has been analyzed in detail to understand the underlying physics of resistive switching phenomenon. Subsequently, a multifilamentary conduction mechanism has been proposed and a “3-D multifilamentary rupturemodel” has been developed in a transition metal oxide-based RRAM. Four different resistance states have been achieved by using three conduction filaments and their subsequent rupture, thus realizing the multiple resistance levels. By varying V\text {STOP} , it has also been verified that the states thus obtained were because of the direct consequence of the conduction filaments. [ABSTRACT FROM PUBLISHER]

A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and electron hopping conduction transports are considered to model the conduction of RRAM. The model can reproduce both the typical I-V characteristics of RRAM in high-/low-resistance state (LRS) and the nonlinear characteristics in LRS. Moreover, to accurately model ac operation mode, the effects of parasitic capacitance and resistance are included in our model. The developed compact model is verified and calibrated by measured data in different HfOx-based RRAM devices under dc and ac operation modes. The excellent agreement between the model predictions and experimental results shows a promising prospect of the future implementation of this compact model in large-scale circuit simulation to optimize the design of RRAM. [ABSTRACT FROM PUBLISHER]

A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau–Lifshitz–Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-inbuilt voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators. [ABSTRACT FROM AUTHOR]