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In this article, the effect of microwave leakage into the diode region on the suppression of backward current in a relativistic backward wave oscillator (RBWO) operating at low magnetic field is investigated by the theoretical analysis, particle-in-cell (PIC) simulation, and experiments. The theoretical results show that some backward electrons are absorbed by the cathode holder due to microwave leakage, and as the microwave power increases, the microwave frequency increases, and the guiding magnetic field decreases, it will promote the absorption of electrons. The PIC simulations based on the first principle reveal that the leakage microwave partially suppresses the backward current and the suppression is enhanced when the incidence TM02 is dominant. In the ${X}$ -band dual-mode RBWO packaged with permanent magnet experiments, a microwave pulse with the power of 3.9 GW, the frequency of 9.93 GHz, and the efficiency of 33% was measured when the diode voltage was 820 kV and diode current was 14.5 kA. [ABSTRACT FROM AUTHOR]

High power microwave (HPM) sources without guiding magnetic field have the advantages of compactness and miniaturization. However, the efficiency is generally limited due to the poor beam quality and low beam transmission rate. Here, we demonstrate a scheme that actually makes use of the large oscillation of electrons in the absence of a magnetic field. In a novel radial three-cavity transit-time oscillator (TTO) with two output ports, about half of the diode current is deposited on the walls of the first two cavities. On the one hand, the truncated electrons are with lower energy, which has delivered some of their kinetic energy to the standing-wave field in the first two cavities. Other electrons then gain energy from the standing-wave field and are accelerated to a much higher beam voltage than the diode voltage. On the other hand, after part electrons are truncated by the first two cavities, the remained electrons are characterized with smaller energy spread, higher current modulation coefficient, which results in a very efficient energy exchange between the beam current and the electromagnetic field in the third cavity with two extraction gaps. Particle-in-cell (PIC) simulation shows that when the diode voltage is 496 kV, beam current is 43.4 kA, the total output microwave powers are 11.4 GW, corresponding to an unprecedented beam-wave conversion efficiency of 53%. [ABSTRACT FROM AUTHOR]

Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs. [ABSTRACT FROM AUTHOR]

The effects of post-\NH3 plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high- \kappa/metal-gate n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and \1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk- and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-\kappa layer. In this paper, appropriate post- \NH3 plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high- \kappa/metal-gate nMOSFET with a Gd cap layer. [ABSTRACT FROM PUBLISHER]

A super klystron-like relativistic backward wave oscillator (RBWO) is presented. In the device, the distributed Cherenkov radiation generated in the slow wave structure (SWS) is absorbed by the electron bunch in the last corrugation and re-accelerated, creating high-energy electrons that overcome the space-charge repulsion force to further compress the bunch length and maximize the fundamental harmonic current, contributing to the extremely efficient microwave generation in the extraction cavity through concentrated transition radiation. A novel elliptical extraction cavity is used to improve the power capacity. A soft magnet is inserted to precisely control the beam path, which provides a higher beam kinetic energy to be extracted and a stronger electric field that interacts with the tighter bunch. In the experiment, as the diode voltage was 585 kV and diode current was 7.5 kA, a microwave pulse with a power of 2.9 ± 0.3 GW measured in the radiation field, a frequency of 8.23 GHz, and a pulse duration of 22 ns was obtained. The corresponding efficiency is up to 66 ± 8%, which is an experimental record for GW-class relativistic vacuum electronic devices. [ABSTRACT FROM AUTHOR]

The complementary field-effect transistor (CFET) with stacked N-type FET (NFET) and P-type FET (PFET) is an attractive approach to shrink the footprint of multiple devices at circuit level and increase transistor density. Compared with traditional device structure, the unique geometry of CFET brings very different parasitics. In this work, we take the inverter as an exemplar CFET circuit building block and provide analytical compact models of calculating parasitic capacitance, which is critical to enable fast and accurate simulations at circuit level. The validity of the models is calibrated and verified with 3-D numerical simulations. A comparison between the CFET inverter with its same ground-rule gate-all-around FET (GAAFET) counterpart reveals the critical CFET design parameters and demonstrates performance advantage of CFET architecture. [ABSTRACT FROM AUTHOR]

A novel integration scheme of postgate single diffusion break (PG-SDB) has been proposed to enhance channel stress for Si gate-all-around (GAA) nanosheet field-effect transistors (NS-FET), based on TCAD simulations. Compared to conventional SDB and self-aligned SDB (SA-SDB), the proposed PG-SDB scheme implements SDB module after the replacement metal gate (RMG) process, so as to eliminate the stress relaxation to free surfaces. The channel stress has been boosted to +3.5 GPa/−4.7 GPa, for N/P NS-FETs, respectively. As a result, great drive capability as well as N/P current matching has been achieved in the PG-SDB GAA NS-FETs. [ABSTRACT FROM AUTHOR]

The temperature dependence of high-frequency noise characteristics for deep-submicrometer bulk and silicon-on-insulator (SOI) MOSFETs has been experimentally examined in this paper. With the downscaling of the channel length, our paper indicates that the power spectral density of the channel noise (Sid) of the bulk MOSFET becomes less sensitive to temperature due to the smaller degradation of the channel conductance at zero drain bias gd0 as temperature rises. We also show that the SOI-specific floating-body and self-heating effects would result in higher white-noise gamma factor. Finally, for both the bulk and SOI MOSFETs, since transconductance gm significantly decreases as temperature increases, their minimum noise figure \NF\min and equivalent noise resistance Rn would degrade with increasing temperature. [ABSTRACT FROM AUTHOR]

For the first time, the high-frequency noise behavior of tensile-strained n-channel metal–oxide–semiconductor field-effect transistors, including their temperature dependency, is experimentally examined. Our experimental results show that with similar saturation voltages, the strained device is found to have larger channel noise than the control device at the same bias point. For given direct-current power consumption, however, due to enhanced transconductance, the strained device has better small-signal behaviors (higher ft and f\max) and noise characteristics (smaller NF\min and Rn) than the control device. [ABSTRACT FROM PUBLISHER]

The dc and high-frequency performance of p-type polycrystalline silicon (poly-Si) finlike thin-film transistors (FinTFTs) with various wide drain region designs are investigated herein. The poly-Si FinTFT with the triangular wide drain design exhibits a high ION/IOFF current ratio (<107) and high cutoff frequency (ƒT= 371.5 MHz at VDS = −1 V). This structure has lower drain series resistance Rd than does the conventional poly-Si FinTFT and lower gate-to-drain capacitance Cgd than does the poly-Si FinTFT with the hybrid wide drain design. This result indicates the possible use of poly-Si TFT technology for radio frequency integrated circuits and the great potential for future use in 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of fin width (Wfin\rm s=15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various Wfin\rm s is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as Wfin is reduced. A thinner Wfin FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest Wfin FinFET possesses the largest bulk oxide trap density (NBOT) than that of a thicker Wfin FinFET. Moreover, the noise of the thinnest Wfin (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest Wfin FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI. [ABSTRACT FROM PUBLISHER]