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To simulate semiconductor devices and circuits working at high frequencies or under a large signal input and to better understand their physical effects, a physically based simulation method is proposed in this paper. It utilizes a physical-model-based field simulation to analyze the semiconductor devices in a circuit and incorporates the field simulation into an equivalent-model-based circuit simulation to simulate the circuit. For the field simulation, a genetic-algorithm-based curve-fitting approach is proposed to extract the parameters of the semiconductor devices’ physical models. The proposed method is employed for the analysis of a few circuits containing a commercial p-i-n diode with model number mot_bal99lt1. The feasibility and accuracy of the proposed method are validated through a comparison of its simulation results with the measurement data, and good agreement is observed. The other merits of the proposed method are also illustrated, including its ability to provide useful physical mechanisms for the better understanding of the behavior of the p-i-n diode under various working conditions. [ABSTRACT FROM PUBLISHER]

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. [ABSTRACT FROM PUBLISHER]

Two compact models for single-electron memory (SEM) are proposed and validated by comparisons with the program SIMON. The approach is based on the master equation method and the orthodox theory. The specific and efficient algorithms for each model are presented. The first model is static and allows directly calculating the final number of electrons on the memory dot. The second model is dynamic, which evaluates every electron tunnel event to assess the stored charge variation and determines the writing or retention times. Both static and dynamic models are written in Verilog-A language and implemented in IC design framework. These SEM models are attractive for circuit simulation to find out the optimal biasing strategy and memory architecture. [ABSTRACT FROM PUBLISHER]

We present a compact model to calculate the capacitance of undoped high-mobility low-density-of-states materials in double-gate device architecture. Analytical equations for estimating the subband energies, while taking the effect of wavefunction penetration into the gate oxide and the effective mass discontinuity, are presented for the first time in a compact modeling framework. The surface potential equation for a two subband system is solved, assuming Fermi–Dirac statistics, and compared to numerical Schrodinger–Poisson simulations. The importance of accurately treating the charge profile distribution is illustrated, and an analytical expression for the effective oxide thickness to model the charge centroid is developed. [ABSTRACT FROM AUTHOR]

This brief presents a novel scaling theory for fully depleted, multiple-gate (MG) MOSFET. The scaling theory is derived from the equation for effective number of gates (ENGs), ENGQG=ENGDG,1+ENGDG,2 where the MG device can be genuinely broken into two equivalent double-gate (DG) transistors working in parallel based on the perimeter-weighted-sum method. Numerical device simulation data for drain-induced-barrier-lowering were compared with the model to validate the formula. Using the scaling theory, the minimum effective channel length improvement factor of \rhoMG=1-(\rm ENGDG/\rm ENGMG)^1/2 shows an improvement of up to 30% in the minimum effective channel length for the MG MOSFET in comparison with DG MOSFET. [ABSTRACT FROM PUBLISHER]