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For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

Nonvolatile logic computations are of particular interest due to their zero standby leakage power consumption. In this paper, we explore a nonvolatile majority logic using voltage-driven magnetoelectric (ME) switching of ferromagnets. Specifically, we employ ME magnetic tunnel junctions (ME-MTJs) connected in parallel to construct a majority gate. We also present the cascadability of the proposed majority gate using CMOS inverters. Furthermore, through a mixed-mode simulation framework consisting of magnetization dynamics and electron transport model, we analyze the robustness of the proposed majority gate under process variations. Our analysis shows that due to parallel connection of the ME-MTJs, high tunnel magnetoresistance (TMR) ratios are required for proper functioning of the proposed majority gate, in presence of variations. In order to relax the constraints on the TMR requirements, we present an alternate implementation of the majority logic that does not require a parallel connection of ME-MTJs, thereby increasing the robustness against process variations. Energy and delay metrics are presented for a full adder implementation using the proposed majority gates. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications. [ABSTRACT FROM PUBLISHER]

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel logic device (SkyLogic) based on skyrmions that are magnetic vortex-like structures having low depinning current density and are robust to defects. A charge current sent through a polarizer ferromagnet (P-FM) nucleates a skyrmion at the input end of an intragate FM interconnect with perpendicular magnetic anisotropy (PMA-FM). The output end of the PMA-FM forms the free layer of an magnetic tunnel junction (MTJ) stack. A spin Hall metal (SHM) is placed beneath the PMA-FM. The skyrmion is propagated to the output end of the PMA-FM by passing a charge current through the SHM. The resistance of the MTJ stack is low (high) when a skyrmion is present (absent) in the free layer, thereby realizing an inverter. A framework is developed to analyze the performance of the SkyLogic device. A circuit-level technique is developed that counters the transverse displacement of skyrmion in the PMA-FM and allows the use of high current densities for the fast propagation. The design space exploration of the PMA-FM material parameters is performed to obtain an optimal design point. At the optimal point, we obtain an inverter delay of 434 ps with a switching energy of 7.1 fJ. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

This paper deals with the monolithic integration of a multiphase generic static power converter (dc/ac or ac/dc). The integration aims at minimizing wire bonds in order to improve the electrical performance as well as the reliability of power converters. To that end, three multiterminal monolithic power Si chips are devised and extensively studied by 2-D simulations. The first power chip integrates the reverse-conducting IGBT devices that compose the high-side part of the converter circuit. This chip is called the common anode and is validated through experimental realizations. The second power chip integrates the reverse-conducting IGBT devices that compose the low-side part of the converter. This chip is called the common cathode chip. The common anode and cathode power chips are judiciously packaged on a Printed Circuit Board substrate over which an insulating Kapton film is laid and through which window openings are realized. The partial flip-chip packaging, of the two power chips, enables the realization of a compact power H-bridge converter with the lowest stray inductance. The third chip integrates the power converter within a single silicon chip and, consequently, eliminates wire bonds. It is considered as the ultimate integration approach. The latter is validated on a monolithic H-bridge inverter by using Sentaurus mixed-mode 2-D numerical simulations. [ABSTRACT FROM AUTHOR]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]

Write time is a critical component of memory performance, which often defines cycle time. In order to accurately predict static random access memory (SRAM) performance, it is also important to take temporal degradation effects into account. This paper investigates the influence of bias temperature instability induced transistor degradation on a dynamic write performance of 20 nm bulk CMOS SRAM. The circuit simulations are based on the comprehensive physical simulation of the aging process and on a very accurate statistical compact model extraction and generation technology. Several scenarios, which differ based on aging pattern of the cell, are investigated to identify the most important transistors and the corresponding critical aging conditions. Mismatch between the two inverters results in an imbalance of the cell, which enlarges the difference in write time between 0 and 1. Finally, we show a response surface of changes in write margin in response to different degradation levels in the ON and OFF transistors. [ABSTRACT FROM PUBLISHER]

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates. [ABSTRACT FROM PUBLISHER]

With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV) causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this paper, with emphasis on the propagation delay time of an inverter in 35-nm technology node, we have first introduced a strategy to take SV into account in four existing compact models using different number of statistical sets. For each model under study, we identified effective parameters of analytical equations which can be utilized to replicate the impact of SV. Moreover, we analyzed the statistical distribution and correlation of those effective parameters and their impact on the propagation delay time in each model. The results of these statistical CMs are compared with the accurate “atomistic” model, and it is shown that using this approach we can predict the propagation delay time standard deviation with less than 0.2%, 4.1%, 4.8%, and 4.7% errors in different models. However, the mean values of the propagation delay time stay almost constant even by employing statistical sets of single parameters. Furthermore, we study the impact of changing the load capacitance and the supply voltage on the statistical behavior of four models in the presence of SV. [ABSTRACT FROM AUTHOR]

This paper proposes a pull-up control scheme in the pseudo-CMOS inverter to design a low-power ring oscillator (RO) realized by only n-type transistors. For comparing 11-stages, the proposed RO and the conventional RO are both fabricated by metal-oxide thin-film transistors with the etch stop layer structure. It is measured that the power-delay product of the proposed RO is reduced by more than 50% under the same value of supply voltage. At the same oscillation frequency, the power consumption tends to be reduced by 18% as oscillation frequency increases. Furthermore, the peak-to-peak voltage of the proposed RO can almost receive a full swing at any supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate, for the first time, 3-D Monolithic integration of short-channel replacement metal gate InGaAs n-FinFETs on fully-depleted silicon-on-insulator CMOS, with TiN/W interlayer contacts. Top layer InGaAs nFETs feature raised source-drain and bottom layer CMOS has Si raised source-drain for nFETs, SiGe raised source-drain for pFETS, implants, silicide, and TiN/W plug contacts. Scaled gate length (Lg) of 15 nm is achieved on bottom layer Si n- and pFETs, while the top layer InGaAs n-FinFETs are scaled to Lg of 25 nm. A densely integrated 3-D 6T-static random access memory circuit with planar InGaAs nFETs stacked on Si pFETs is demonstrated by taking advantage of the interlayer contacts. This yields significant area reduction when compared with 2-D layouts. [ABSTRACT FROM AUTHOR]

The applications of a-InGaZnO thin-film transistors (TFTs) to logic circuits have been limited owing to the intrinsic n-channel operation. In this paper, we demonstrated a hybrid inverter constructed by p-channel low-temperature poly-silicon (LTPS) TFTs and n-channel amorphous-indium–gallium–zinc–oxide (a-IGZO) TFTs. Hydrogenated LTPS TFTs and a-IGZO TFTs have been successfully fabricated on the same panel, followed by a rapid thermal annealing treatment to remove the hydrogens in the a-IGZO TFTs. The resulted hybrid inverter exhibits large noise margin closed to V\textsf {DD}/\textsf {2} and a high voltage gain as 68.3. Due to the complementary configurations in the static state, the inverter shows small current and thus consumes low power in hundreds of picowatts. As all the fabrication processes are compatible with conventional techniques, the reported results may open new opportunities in circuit design and applications for oxide TFTs. [ABSTRACT FROM PUBLISHER]

Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design. [ABSTRACT FROM PUBLISHER]

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero- \(\textit {V}_\mathbf {GS}\) -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic circuits. [ABSTRACT FROM AUTHOR]

During recent years, high- \(k\) spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual- \(k\) spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in. [ABSTRACT FROM AUTHOR]

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of work function, with due attention to the design of logic gates, such as NOT, NAND, NOR, and XOR. Results demonstrate that optimum work function is 4.7 eV in which the highest value of I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} can be achieved. Mixed-mode simulations are used to determine the performance of the proposed logic gates. Also, the proof regarding the mitigation of the total power consumption up to 56% is presented so that not gate based on S-FED improves power delay product by about 30%, compared with the CMOS-based version. A similar fabrication process with the CMOS technology could be asserted as the considerable advantage to pave the way of feasibly realizing the new generation of S-FED-based logic gates. [ABSTRACT FROM AUTHOR]

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness t\mathrm{ si} , thick gate oxide thickness t\mathrm{ ox} , and short channel length Lg , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope \eta and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage V_{\mathrm{ dd,min}} for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of −2.3–1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability. [ABSTRACT FROM AUTHOR]

In this paper, a novel superjunction (SJ) MOSFET embedded with an ultrasoft reverse-recovery body diode is proposed and studied by simulation. The device has a composite assistant layer, which consists of a highly doped n-buffer region and an extended p-pillar region, under the SJ layer. The assistant layer provides residual carriers during the reverse-recovery procedure and smoothens the current. Simulated results show that the soft factor is upgraded from 0.04 to over 0.3 when the depth of the assistant layer increases from $0~\mu \text{m}$ to that of the SJ layer. The increment of the specific ON-resistance is less than 10% if the concentration of the n-buffer region is 25 fold that of the n-pillar region. [ABSTRACT FROM AUTHOR]

From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures—in the example of NAND and NOR gates—which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption. [ABSTRACT FROM AUTHOR]

The flexible electronics is promising in the area of the Internet of Things and wearable devices and the thin-film transistor (TFT) technologies are crucial for flexible electronics. Among them, the zero- V\text {GS} load TFT circuits are widely used for its simple structure and high gain merits. However, the yield model is lacking for zero- V\text {GS} load TFT circuits. In this paper, the analytical noise margin model for the zero- V\text {GS} load TFT NAND gate and NOR gate is derived. Based on that, a simple, accurate, and highly scalable yield model for the combinational TFT logic circuits based on standard cell library is further proposed. ISCAS’85 benchmark circuits are used to validate the yield model. Compared with Monte Carlo simulation, the model achieves 3–4 orders of magnitude speedup with comparative results. [ABSTRACT FROM AUTHOR]

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation. [ABSTRACT FROM AUTHOR]

High- $k$ spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high- $k$ spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high- $k$ spacer material. An asymmetric dual- $k$ spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high- $k$ spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high- $k$ FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations. [ABSTRACT FROM AUTHOR]

Advanced power module technology capable of taking advantage of the superior features of next-generation power devices, such as those fabricated with SiC and GaN, must be developed to create much more compact and cost-effective power conversion systems. New power modules based on such technology are especially required to allow fast switching of power devices in the extended junction temperature range. This paper describes the major technical challenges involved in sufficiently improving the thermal stress reliability of the critical package systems in SiC power modules and in markedly reducing internal parasitic inductance. Thermal stress reliabilities of the die attachment system, wire bonding system, and encapsulant system are successfully improved, all of which are shown to be able to achieve common life targets: 1) 3000 h for a storage test at 250 °C and 2) 3000 cycles for thermal cycling between −40 °C and 250 °C. A novel phase-leg power module capable of substantially reducing the loop inductance along the principal current tracks is proposed and fabricated by applying SiC-JFETs, SiC-Schottky barrier diodes, and the abovementioned reliable thermal stress package systems. Double pulse switching testing of the module reveals smaller drain-source voltage spikes and ringing even in turn-ON and turn-OFF transients at very high slew rates of current and voltage. Finally, a 0.34 L forced-air-cooled dc 600 V input ac 50 Hz 400 V 25 kW output three-phase SiC inverter is fabricated using three-phase leg modules and its operation is demonstrated at high-power levels. [ABSTRACT FROM AUTHOR]

In this paper, we explore the design space of two possible candidate FETs for sub-10-nm technologies—FinFET like double gate MOSFETs (DGFETs) and Schottky-barrier (SB) devices. Though SB devices are expected to have lower ON current, their lower source/drain resistance ( RS/\!D ) can be important in scaled technologies. We evaluate the suitability of the optimized devices for logic and memory designs in the sub-10-nm technologies using a comparative device-circuit analysis based on nonequilibrium Green’s function-based transport models and HSPICE circuit simulation. The devices are optimized with gate-to-source ( $S$ )/drain ( $D$ ) underlap, and proper body thickness to suppress direct source-to-drain tunneling (DSDT). Our analysis shows that introduction of gate-to- $S/\!D$ underlap provides the benefit of reducing DSDT, while reduced body thickness provides a tradeoff between low DSDT and high RS/\!D . Results also show that DGFETs provide higher drive strength even with larger RS/\!D . As a result, DGFET-based logic shows higher performance, and better read stability for memory while SBFET-based memory shows higher write stability. [ABSTRACT FROM AUTHOR]

Solution-driven metal–oxide semiconductors have recently received much attention as a viable option for low-cost, flexible electronic devices. In this paper, a simple, environmentally friendly aqueous solution method has been adopted to deposit an ultrathin In2O3 semiconductor layer with a thickness of about 7 nm at low temperature. Then, in combination with the advantages of atomic layer deposition (ALD) technology, an ultrathin aluminum oxide dielectric layer of about 20 nm was prepared to fabricate high-performance In2O3/Al2O3 thin-film transistor (TFT) devices. The device with optimized annealing temperature of 280 °C has demonstrated an excellent electrical performance, including a high saturation mobility of 11.85 cm2 · V−1 · s−1, a large ON/OFF current ratio of 106, a low threshold voltage of 0.12 V, a small hysteresis voltage of 0.05 V, and a small density of interface state of $\textsf {1.97} \times \textsf {10}^{\textsf {12}}$ cm−2, respectively. To demonstrate the potential of In2O3/AlOx TFT toward more complex logic applications, the unipolar inverter was further constructed and exhibited a high gain of 5. Importantly, all these device parameters were obtained at an ultralow operating voltage of 2.5 V. As a result, it can be inferred that the water-induced In2O3 TFTs based on ALD-derived Al2O3 dielectrics have a potential application as a promising alternative for low-cost, low-power consumption, and large-area environmentally friendly oxide flexible electronics. [ABSTRACT FROM AUTHOR]

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts. [ABSTRACT FROM AUTHOR]

Previously reported thin-film transistor (TFT) digital logic gates are mostly static circuits. If the static logic circuits are implemented using either nMOS or pMOS technologies alone, unlike CMOS technologies, the circuits consume high power because of the steady-state current, and take large circuit area. In this paper, the dynamic logic circuits using n-type a-IGZO TFTs are proposed to resolve the power and circuit area issues. The dynamic logic circuits such as inverters and nand gates are fabricated in an amorphous indium–gallium–zinc–oxide TFT technology, and traditional static logic circuits are also implemented with the same technology for comparison purposes. The measurement results show that the proposed dynamic logic circuit consumes no steady-state current, and the circuit area is reduced by 93.1%. [ABSTRACT FROM PUBLISHER]

We investigate the performance of hysteresis-free short-channel negative-capacitance FETs (NCFETs) by combining quantum-mechanical calculations with the Landau–Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of drain-induced barrier lowering is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance in the output characteristics of the NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresis-free NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter. [ABSTRACT FROM PUBLISHER]

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits. [ABSTRACT FROM AUTHOR]

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the ID – VG distribution at various V\mathrm{ DS} values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full ID – VG distribution rather than just VT distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current ( I\mathrm{ READ} ) to show excellent accuracy. The method also shows a $30\times $ improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method. [ABSTRACT FROM AUTHOR]

In this paper, the insertions of dielectric in metal/insulator/semiconductor contacts are considered via their associated impact on the dc and ac performances. Based on dc output characteristics projections, we found that single insertion and/or single-metal integration schemes are unlikely to result in simultaneously successful Fermi-level pinning alleviation on both n and pFETs. We show that the added C\mathrm { {MIS}} contributes to a significant extra improvement in terms of intrinsic inverter delay. In particular, an optimal configuration consisting of Pt-liner/ p-Si and Zr/TiO2(15Å)/n-Si contacts can lead to a ring oscillator frequency higher than that of p and nFETs each flanked by ideal ohmic contacts with 10^-9~\Omega \cdot \mathrm cm^2 resistivity. [ABSTRACT FROM AUTHOR]

We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI substrate, with the novel recessed channel and source/drain structures. Various channel lengths ( L\mathrm {ch} ) from 500 to 30 nm and channel thicknesses ( T\mathrm {ch} ) from 90 to 10 nm are implemented into the Ge CMOS devices and comprehensive geometry dependence analysis is carried out in terms of both L\mathrm {ch} and T\mathrm {ch} . With shrinking T\mathrm {ch} , the gate electrostatics are enhanced significantly but the on-state performance is found to be deteriorated simultaneously. It is also confirmed that Ge nMOSFETs are more sensitive to T\mathrm {ch} than pMOSFETs due to the phosphorus diffusion inside Ge. CMOS circuits, such as inverters, NANDs, NORs, and ring oscillators, are further investigated. [ABSTRACT FROM PUBLISHER]

In this paper, based on a full intrinsic–extrinsic model for symmetric doped double-gate MOSFET, we analyze the impact of FinFET gate resistance over the inverter and ring oscillator performance. It is shown that, when the total number of fins remains constant, the propagation delay can be improved thanks to the multifinger configuration that translates into the gate resistance reduction. Furthermore, the fin spacing in addition to source/drain fin extension reduction are of primary importance to improve the digital circuit performance. [ABSTRACT FROM PUBLISHER]

An analytical model is presented to understand the time response of an inverter to ionizing particles based on physical equations. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state nMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state nMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state pMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state pMOS resistance, doping concentration of P-region in the diode, and the photocurrent pulse are scrutinized. [ABSTRACT FROM AUTHOR]

The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in the subthreshold region with no extra energy cost. The optimum pMOS-to-nMOS width ratio is obtained and compared through three approaches: 1) finding the maximum current-over-capacitance ratio of a biased transistor; 2) deriving an analytical expression by minimizing the delay of an inverter; and 3) simulating different CMOS logic gates in the subthreshold region. Simulation results illustrate that in the subthreshold region, the frequency attains its maximum at the optimum pMOS-to-nMOS width ratio independent of the supply voltage. Using this optimum value in designing a carry-look-ahead adder improves the propagation delay, energy consumption, and energy-delay product by up to 33%, 36%, and 57%, receptively, compared with when the conventional pMOS-to-nMOS width ratio (in the superthreshold region) is used. We verified our analytical model by performing circuit simulations in four CMOS technologies (TSMC 180 nm, IBM 130 nm, TSMC 90 nm, and ST 65 nm). [ABSTRACT FROM PUBLISHER]

In this paper, high-gain hybrid complementary inverter was first designed and fabricated by coupling cosputtered ZnSiSnO and solution-processed semiconducting single-walled carbon nanotubes (SWCNTs). Field-effect transistors with ZnSiSnO and SWCNT networks show high electrical performance and acceptable bias stability. ZnSiSnO thin-film transistor shows field-effect mobility of 11.6 cm2/ $\text {V}\cdot \text {s}$ , threshold voltage of 0.98 V, and subthreshold swing of 0.18 V/decade. The corresponding values for the SWCNT transistor are 10.2 cm2/ $\text {V}\cdot \text {s}$ , 0.59 V, and 0.21 V/decade, respectively. The ZnSiSnO/SWCNT inverter shows excellent performance with a voltage gain of 41.5, a high noise margin of 2.62 V, and a low noise margin of 1.86 V at a small ${V}_{\text {DD}}$ of 5 V. The peak consumption is only $3.2\times 10^{8}$ W at ${V}_{\text {DD}} = 5$ V. Our finding underscores the coupling of cosputtered ZnSiSnO and solution-processed semiconducting SWCNT as an alternative strategy to the high-performance inverter development and has the potential for widespread technological applications. [ABSTRACT FROM AUTHOR]

Hyper-FET, an emerging device with unconventional characteristics, exhibits sub-kT/q switching and can attain higher ON current ( I \mathrm{\scriptscriptstyle ON} ) than standard FinFETs with matched OFF current ( I \mathrm{\scriptscriptstyle OFF} ). In continuation to the insights on the device level design methodology conveyed in part I [1], here we analyze the circuit implications of the unique characteristics of Hyper-FETs, such as hysteresis and abrupt switching. We provide a comprehensive discussion on the design of Hyper-FET-based circuit primitives, such as inverter, NOR and NAND gates. We emphasize on tailoring the hysteresis to avoid functional failure in logic circuits and deduce the correspondence between hysteresis observed in the device and circuit characteristics. To complement the device level constraints presented in part I, here we present additional stringencies for material parameters to aid in designing Hyper-FET-based logic gates with regenerative property and rail-to-railswing. Our analysis indicates that, at low V\sf DD (<0.3 V), properly designed Hyper-FET-based inverters can exhibit 25%–68% less energy at iso-delay (compared with FinFET-based CMOS inverters). We also provide targets for future material exploration. [ABSTRACT FROM AUTHOR]

A two-point expression of effective drive current ( Ieff\PG) for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of Ieff\PG estimates the PG latency with a reasonable accuracy (relative error <15%) under different technology nodes from 90 to 20 nm and a wide range of biasing conditions including gate overdrive voltage up to 0.4 V and nonzero body bias between −0.3 and 0.3 V. The effective drive current expression is simple to use, independent of process technologies, and maintains accuracy when transistors are scaled down to deep submicron regime with severe nonidealities such as drain-induced barrier lowering. Ieff\PG provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( Ieff\inv) is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of Ieff\PG is discussed, which illustrates the Ieff\PG does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( Ieff\inv) do. [ABSTRACT FROM PUBLISHER]

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III–V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type $I$ – V\text{s} , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed. [ABSTRACT FROM PUBLISHER]

A highly tunable oscillator using magnetic tunnel junctions (MTJs) has been developed through integration with CMOS ring oscillators. MTJs are used to replace the pMOS transistors in a typical CMOS inverter fabricated in 40-nm CMOS. The hybrid MTJ-CMOS devices exhibit a voltage-controlled oscillator gain of 300–500 MHz/V and are tunable with respect to both voltage and magnetic field. [ABSTRACT FROM AUTHOR]

Organic complementary circuitry combines all the advantages of plastic electronics, such as flexibility, thinness, and solution processability with low power consumption. Here, we report organic complimentary inverters fabricated in a carrier-free batch process on a plastic foil with dielectric and semiconductor layers patterned using the high-volume gravure contact printing technique. The transistor components have bottom-gate, bottom-contact configuration with aluminum gates and gold contacts, allowing full use of photolithographic processing while protecting the semiconductors by depositing them last. Cross-linkable polymer dielectric, p-type small molecule and n-type polymer semiconductors are printed from inks based on nonchlorinated solvents. Printing instability is observed for capillary numbers approaching 1. The 430-nm-thick dielectric affords a relatively low operational voltage, and it is the thinnest printed organic dielectric reported in the literature for organic inverters to date. Both p- and n-type transistors have a mobility of 0.01–0.04 cm ^2\textV^\mathrm -1\texts^\mathrm -1 . The device parameters for the n-type transistors show less variation than the p-type transistors, which can be related to the more isotropic charge transport in polymer films compared with the small-molecule polycrystalline films. The resultant inverters have an average gain of 4.5 ± 1.5 and a maximum gain of 8 at V\mathrm {DD} =-20 V. The combination of the conventional photolithographic processing and gravure contact printing can therefore be used to fabricate bottom-gate organic complementary circuitry on plastic. [ABSTRACT FROM AUTHOR]