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In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation. [ABSTRACT FROM AUTHOR]

In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [ABSTRACT FROM PUBLISHER]

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( \textN\text {S}) and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance. [ABSTRACT FROM PUBLISHER]

In this paper, we develop a statistical model for random telegraph noise (RTN) related low-frequency noise (LFN). With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We clarify why the variability of RTN/LFN does not follow a 1/ $\surd $ area dependence. The model explains the effect of the halo implanted regions on the LFN statistics and the large variability of long channel devices found under certain bias conditions, which can be as large as that of short channel devices. We show that the LFN of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results, we derive that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. We also demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. [ABSTRACT FROM AUTHOR]

Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose and demonstrate a novel technique for true random number generation using commercial off-the-shelf Flashmemory. Flashmemory cells are known to exhibit thermal noise and random telegraph noise during sensing of their threshold voltage. In order to extract this inherent noise properties of the Flash memory bits through a standard digital Flash memory interface, we utilize the program disturb and read noise characteristics, which are fundamental properties of all NAND Flash memory arrays. The proposed technique is experimentally demonstrated and evaluated using state-of-art Flash memory chips. The experimental evaluation shows that the proposed technique enables extraction of high quality, high throughput, controllable (or tunable), and temperature- and aging-tolerant random bits. The random bits generated by the proposed technique pass all tests in the National Institute of Standards and Technology statistical test suite. The advantages of the proposed technique are as follows: 1) it is cost-effective as it does not require any special circuitry or hardware modification; 2) it is tolerant to aging and temperature effects; 3) it is easy to implement in software and to deploy through software updates; and 4) it is widely applicable to all electronic devices utilizing modern NAND Flash memory chips. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V \(_{\rm TH}\) shifts and fluctuations, which are even visible during the I \(_{D}\) –V \(_{G}\) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times \(\tau _{c}\) and \(\tau _{e}\) , and their impact on V \(_{\rm TH}\) as a function of gate voltage V \(_{G}\) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V \(_{G}\) swing and operational temperatures. [ABSTRACT FROM PUBLISHER]

Resistive-switching memory (RRAM) is attracting a widespread interest for its outstanding properties, such as low power, high speed, and good endurance. A crucial concern for RRAM is the current fluctuation, which induces significant broadening of resistance levels in single-bit and multilevel applications. This paper addresses low-frequency fluctuations focusing on $1/f$ and random telegraph noise contributions in intrinsic, i.e., typical, cells. The current fluctuations are studied in both the time and frequency domains, and the analytical models are presented to predict the resistance broadening for different RRAM states. Finally, the resistance dependence of noise and broadening is studied with the support of a 3-D finite-element model. [ABSTRACT FROM AUTHOR]

In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process. [ABSTRACT FROM PUBLISHER]

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center. [ABSTRACT FROM AUTHOR]

Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition ( pdc ), which is traditionally used for RTN characterization, ac trap occupancy probability ( pac ), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on pac . The results show that degradations are highly workload dependent and that pac is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) is widely considered as a disruptive technology. Despite tremendous efforts in theoretical modeling and physical analysis, details of how the conductive filament (CF) in metal-oxide-based filamentary RRAM devices is modified during normal device operations remain speculative, because direct experimental evidence at defect level has been missing. In this paper, a random-telegraph-signal-based defect-tracking technique (RDT) is developed for probing the location and movements of individual defects and their statistical spatial and energy characteristics in the CF of state-of-the-art hafnium-oxide RRAM devices. For the first time, the critical filament region of the CF is experimentally identified, which is located near, but not at, the bottom electrode with a length of nanometer scale. We demonstrate with the RDT technique that the modification of this key constriction region by defect movements can be observed and correlated with switching operation conditions, providing insight into the resistive switching mechanism. [ABSTRACT FROM PUBLISHER]

A low-frequency noise (LFN) analysis technique is introduced, based on the autocorrelation of the LFN spectra in terms of frequency, biasing, and temperature. This technique reveals information about the mechanisms behind 1/ f noise that is difficult to obtain otherwise. These correlation analyses provide strong evidence that the LFN of both nMOS and pMOS transistors is mainly composed of the superposition of thermally activated random telegraph signals (RTSs). The methodology enables quantification and validation of old and new LFN models, and, therefore, helps to clarify the relation between RTS and 1/ f that is still frequently debated in the literature. [ABSTRACT FROM PUBLISHER]

Random telegraph noise (RTN) in trigate nanowire transistors (NW Tr.) is systematically studied with respect to the NW size dependence. Time to capture and emission, which is related to the characteristic of the traps, such as trap energy, is independent of NW size. On the other hand, noise amplitude increases as the NW size decreases showing the similar size dependence to the reported scaled planar Tr. In addition, RTN after hot-carrier injection (HCI) and negative bias stress (NBS) is studied. HCI and NBS induce additional carrier traps, which generate larger noise signals. Since the degradation by HCI or NBS is larger with narrower width, RTN after these stresses is found to be severer in the NW Tr. [ABSTRACT FROM AUTHOR]

The random telegraph noise (RTN) characteristics of high- k (HK)/metal gate (MG) pMOSFETs with uniaxial compressive strain have been investigated. The configuration-coordinate diagram and band diagram are both established by extracting trap parameters, including capture and emission time, activation energy for capture and emission, trap energy level, and trap location in gate dielectric. Through a comparison of RTN results and gate-leakage current density ( J_{G}) between HK/MG pMOSFETs with and without uniaxial compressive strain in channel, it is found that the trap position from the insulator/semiconductor interface is reduced in the uniaxial compressive strained HK/MG pMOSFETs. This is reasonably attributed to the strain-increased tunneling barrier height and out-of-plane effective mass, which brings about the reduction in the tunneling attenuation length. Meanwhile, it can also be demonstrated by the lower J_{G}$ in uniaxial compressive strained HK/MG pMOSFETs. [ABSTRACT FROM AUTHOR]

Multilevel random telegraph noise in gate-all-around silicon nanowire pMOSFET shows gate voltage overdrive-dependent interstate transitions, statistical count of which indicates the existence of oxide traps with different time constants. Following the detail extraction of the capture and emission time with gate bias, both have been found to deviate from the usual trend, as predicted by the conventional Shockley–Read–Hall statistics. Two traps in the gate–oxide have been found, in which the near interface is found to respond through the altered RTN activation energy barrier by spatially varying oxide residual strain energy, whereas the farther responds under the weak influence of the oxide strain energy. On the other hand, the emission time of near interface trap has been found to follow similar strain influenced activation barrier, but the magnitude of the emission time of the farther trap shows the hole emission through the p+ polysilicon gate–oxide interfacial trap, while favored by the electrostatic field in oxide. From RTN distributions and time lag plots, interstate transitions and state suppression in RTN are explained under the framework of two-trap postulate, in order to elucidate the unusual gate bias dependence of the measured trap time constants in silicon nanowire pMOSFETs. [ABSTRACT FROM AUTHOR]

We report on the investigation of random telegraph signals (RTSs) in pMOSFETs at variable temperatures to identify and characterize the hole traps residing at the oxide–semiconductor interface. Attractive center defects as well as a repulsive center defect are identified with trap location, capture cross section, remote Coulomb scattering coefficient, capture barrier energy, trap binding enthalpy, relaxation energy, and change in entropy with hole emission. The attractive centers responsible for RTS were a pair of dissociated three-coordinated silicon (D-III-Si) defects while the repulsive center was identified as a puckered/back-projected oxygen vacancy defect, [a pair of under-coordinated silicon (III-Si) and over-coordinated oxygen (III-O) defects]. Both contain ${E}\gamma ^{\prime }$ centers. This is the first time when such detailed analysis is reported on the hole traps in SiO2 which are responsible for RTS. [ABSTRACT FROM AUTHOR]

The 3-D simulator, which is capable of sensing potential change due to single electron’s movement via a local trap inside the high-K gate-stacking block, is developed. Then, we carefully investigate how the electron’s movement effects on the reliabilities of high-K gate-stack far beyond 10-nm generations. The simulation result shows that the potential change caused by a single electron’s charge is about a few hundered millivolts inside the high-K gate-stacking block. By this result, random telegraph noise (RTN) and trap-assisted tunneling (TAT) are carefully investigated with respect to various applied biases, interface suboxide layer thicknesses, and the dielectric constant of high-K dielectrics (K). We also take into account the Coulomb blockade of a local trap, and then obtain several phase diagrams for distinguishing RTN and TAT under various conditions. It is then found that K = 30 can most effectively suppress the gate leakage current. [ABSTRACT FROM PUBLISHER]

A low-power 2-Mb Resistance random access memory (ReRAM) macro is developed in a 90-nm CMOS platform with a 3-nm-thick TaOx/Ta2O5 switching layer of the active area of 0.01~\mu \textm^2 . Instability of the ON-state minority bits degrades the high-temperature retention lifetime. The oxygen vacancies in the filament are annihilated by oxygen ions, which have been generated mainly by the OFF-write bias repeated in the ON/OFF switching cyclesbefore the retention. This instability is improved by decreasing the oxygen concentration near Ru bottom electrode as well as lowering the OFF-write bias. Instability of the OFF-state minority bits narrows the memory window by random telegraph noise (RTN). Setting a statistically derived guard band with a pulse-modulated verify sequence is able to handle RTN to ensure the memory window. The 2-Mb ReRAMmacro with 1-b error-correcting code is confirmed to ensure ten years’ retention from −40 °C to 85 °C after 1E3 ON/OFF cycles. [ABSTRACT FROM PUBLISHER]

A novel method for the extraction of the lateral position of border traps in nanoscale MOSFETs is presented. Using technology computer-aided design (TCAD) simulations, we demonstrate that the dependence of the trap-induced threshold voltage shift on the drain bias is more sensitive to the lateral trap position than to the impact of random dopants. Based on this, the lateral defect position can be determined with a precision of several percent of the channel length. To demonstrate the correct functionality of our technique, we apply it to extract the lateral positions of experimentally observed traps. Although the most accurate algorithm is based on time-consuming TCAD simulations, we propose a simplified analytic expression, which allows for the extraction of the lateral trap position directly from the experimental data. While the uncertainty introduced by random dopants is <10% for the TCAD model, the additional errors introduced by the simple analytic expression still provide trap positions accurate to 5% for the devices with 20-nm channel length and 20%–25% for 100-nm-long devices. [ABSTRACT FROM AUTHOR]

Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions with both the Si substrate and Poly-Si gate. The model is implemented in a 3-D device simulator to examine the effect of device structure and bias conditions. The conventional analytical model does not precisely estimate the noise powers in short-channel MOSFETs due to the nonuniform trapped charge effect. The high trap density near the shallow trap isolation edges is predicted quantitatively by comparing the measured data with the simulated data. In conclusion, we confirm the validity of the developed unified simulator and its usefulness for gaining insights into trap sites and noise reduction engineering. [ABSTRACT FROM AUTHOR]

An on-chip variability characterization system implemented in a 45-nm CMOS process is used for direct time-domain measurements of random telegraph noise (RTN) in small-area devices. A procedure for automated extraction of RTN parameters from large volumes of measured data is developed. Statistics for number of traps, NT, and single-trap amplitudes, ΔVth, are studied across device polarity, bias, and gate area. A Poisson distribution is used to model NT and a log-normal distribution is used to model ΔVth. The scaling of the two statistics across gate dimensions is discussed; the expected value of NT is shown to scale with (L - ΔL)-1, whereas the expected value of AVth is shown to scale with W-1(L - ΔL)-0.5. The two statistics are combined in a compact RTN probabilistic model representing the statistics of the overall ΔVth fluctuations because of RTN. This model is demonstrated to give accurate predictions of the tails of the measured RTN distributions at the 95th percentile level, which scale with W-1(L - ΔL)-1.5. A comparison between nMOS and pMOS devices shows that pMOS devices exhibit both a higher average number of traps and a larger average single-trap ΔVth amplitude, leading to a comparatively larger overall impact of RTN. [ABSTRACT FROM AUTHOR]

1/f noise is a fluctuation in the conductance of semiconductors and metals. This noise could be a fluctuation in the number of free electrons or in their mobility. Many experimental studies have proved that the 1/f noise in homogeneous samples is a fluctuation in the mobility. There is a reliable empirical relation for the power density of the mobility noise. Theoretical models for mobility noise have not had much influence in the discussions. The theoretical position for number fluctuations is quite the opposite. The generally accepted McWhorter model is simple; however, very few experimental studies definitely prove number fluctuations and exclude uncorrelated mobility fluctuations. There is an extensive literature on noise in MOSTs. Submicrometer MOSTs are notorious for their high low-frequency noise. Almost all studies start from the McWhorter generation-recombination (GR) model. The discussion is confused by the many complications of the MOSTs, such as mobility degradation, surface and contacts effects, size of the samples, etc. An additional problem is that the real 1/f noise is often mixed up with other types of low-frequency noise, such as burst and GR noises. A critical discussion is given for the Kirton and Uren model. Analytical expressions are presented for the results of their computer simulations. This explains their surprising discovery that the density of McWhorter states may be "substantially" different from the usual 1/T distribution. [ABSTRACT FROM AUTHOR]