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This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. [ABSTRACT FROM PUBLISHER]

In this paper, the effect of negative-capacitance (NC) on germanium FinFET (GeFinFET) with the presence of fixed trap charges (${N}_{\text {ftc}}$) has been studied. The analysis of various parameters of NCGeFinFET has shown that the positive trap charges improve the device characteristics whereas the negative trap charges (NTC) degrade the performance of devices. Therefore, we have optimized properties of ferroelectric (FE) to suppress the degradation caused by NTC. Furthermore, the impact of ${N}_{\text {ftc}}$ has been studied on the output characteristics of NCGeFinFET inverter, and it has been shown that the degradation due to NTC reduces by optimizing the FE properties. It has also been demonstrated that NCGeFinFET exhibits excellently improved characteristics as compared to GeFinFET. [ABSTRACT FROM AUTHOR]

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reported is updated to account for the subthreshold regime and is used to simulate a zero- $V_{{\rm GS}}$ inverter (one of the most basic unipolar logic gate). Based on the extracted noise margins, two methodologies were studied to assess the potential of this technology in terms of p-logic digital circuits. The first one is De Vusser's V_{T} -based method that we adapted to our OTFT model. The second one relies on statistical modeling and takes into account the actual worst case scenario for an inverter in terms of noise margins. It better represents the experimental distribution because of specific corner models. The different analysis studied in this paper shows that these OTFTs, in the current state of the technology, are still not ready for complex digital circuits as the throughput is expected to be quite low. In addition, the proposed methodology and related interpretation are technology-independent therefore this analysis may serve as a basis to characterize unipolar-logic printed electronics and can be further extended to complementary-logic circuits. [ABSTRACT FROM PUBLISHER]

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family. [ABSTRACT FROM AUTHOR]

The applications of a-InGaZnO thin-film transistors (TFTs) to logic circuits have been limited owing to the intrinsic n-channel operation. In this paper, we demonstrated a hybrid inverter constructed by p-channel low-temperature poly-silicon (LTPS) TFTs and n-channel amorphous-indium–gallium–zinc–oxide (a-IGZO) TFTs. Hydrogenated LTPS TFTs and a-IGZO TFTs have been successfully fabricated on the same panel, followed by a rapid thermal annealing treatment to remove the hydrogens in the a-IGZO TFTs. The resulted hybrid inverter exhibits large noise margin closed to V\textsf {DD}/\textsf {2} and a high voltage gain as 68.3. Due to the complementary configurations in the static state, the inverter shows small current and thus consumes low power in hundreds of picowatts. As all the fabrication processes are compatible with conventional techniques, the reported results may open new opportunities in circuit design and applications for oxide TFTs. [ABSTRACT FROM PUBLISHER]

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero- \(\textit {V}_\mathbf {GS}\) -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic circuits. [ABSTRACT FROM AUTHOR]

During recent years, high- \(k\) spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual- \(k\) spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in. [ABSTRACT FROM AUTHOR]

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of −2.3–1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability. [ABSTRACT FROM AUTHOR]

This paper proposes an optimization method with a high degree of freedom for the doping profile optimization of power devices. In this method, which is based on topology optimization, the design domain is divided into many elements, and the doping or dose densities of all of the elements are taken as the design variables to be optimized. An optimal structure is obtained by repeatedly modifying a given structure using mathematical programming. The proposed optimization method was applied to two design problems. First, the tradeoff between the breakdown voltage and ON-resistance was optimized for a p-n diode by using a function of the electric field strength as the objective function under a constraint to the ON-resistance. Second, for a junction termination extension structure, a robust optimization method considering the ion implantation process was applied to prevent the concentration of the electric field by dose fluctuation. The numerical results from these two problems demonstrate that the proposed method can be effectively used to derive an improved doping profile for power devices. [ABSTRACT FROM AUTHOR]

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies. [ABSTRACT FROM AUTHOR]

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation. [ABSTRACT FROM AUTHOR]

Solution-driven metal–oxide semiconductors have recently received much attention as a viable option for low-cost, flexible electronic devices. In this paper, a simple, environmentally friendly aqueous solution method has been adopted to deposit an ultrathin In2O3 semiconductor layer with a thickness of about 7 nm at low temperature. Then, in combination with the advantages of atomic layer deposition (ALD) technology, an ultrathin aluminum oxide dielectric layer of about 20 nm was prepared to fabricate high-performance In2O3/Al2O3 thin-film transistor (TFT) devices. The device with optimized annealing temperature of 280 °C has demonstrated an excellent electrical performance, including a high saturation mobility of 11.85 cm2 · V−1 · s−1, a large ON/OFF current ratio of 106, a low threshold voltage of 0.12 V, a small hysteresis voltage of 0.05 V, and a small density of interface state of $\textsf {1.97} \times \textsf {10}^{\textsf {12}}$ cm−2, respectively. To demonstrate the potential of In2O3/AlOx TFT toward more complex logic applications, the unipolar inverter was further constructed and exhibited a high gain of 5. Importantly, all these device parameters were obtained at an ultralow operating voltage of 2.5 V. As a result, it can be inferred that the water-induced In2O3 TFTs based on ALD-derived Al2O3 dielectrics have a potential application as a promising alternative for low-cost, low-power consumption, and large-area environmentally friendly oxide flexible electronics. [ABSTRACT FROM AUTHOR]

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts. [ABSTRACT FROM AUTHOR]

In this paper, all-solution-processed low-voltage (<3~V) organic thin-film transistor inverters on polyethylene naphthalate plastic substrate were achieved in the bottom-gate bottom-contact device configuration. In the devices, 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene was used as the channel layer, and ultraviolet cross-linked polyvinyl alcohol was used as the gate dielectric layer. With optimized inkjet jetting process parameters and a proper polymer dielectric substrate surface, fine silver electrodes were formed as the source, drain, and gate electrodes. The maximum processing temperature was 150^\circC. The devices show promising performance with a mobility of 0.8 cm^2/(V\cdots), a subthreshold swing of 100 mV/decade and an ON/OFF ratio of about 10^4. The fabricated diode-load inverter has a high dc voltage gain up to 67.3 at a supply voltage of 3 V. [ABSTRACT FROM AUTHOR]

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits. [ABSTRACT FROM AUTHOR]

An analytical model is presented to understand the time response of an inverter to ionizing particles based on physical equations. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state nMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state nMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state pMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state pMOS resistance, doping concentration of P-region in the diode, and the photocurrent pulse are scrutinized. [ABSTRACT FROM AUTHOR]

An equivalent circuit model of monolithic 3-D inverter (M3INV) considering the electrical coupling between the stacked metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. We conduct the parameter extraction with technology computer-aided design (TCAD) simulations, where LETI-UTSOI model in HSPICE is used for the bottom PFET and the top NFETs. Their parameters are extracted by fitting their current–voltage (for dc analysis) and capacitance–voltage (for transient ac analysis) characteristics. The parameters extracted from the LETI-UTSOI model contain the electrical coupling at the gate of the bottom MOSFET. In order to extract external capacitances such as monolithic intertier via (MIV)-to-MIV and MIV-to-contact in M3INV, we use two structures, the first that contains MIVs and metal lines and the second that does not. We observe that the dc and transient characteristics of M3INVs built using our extracted parameters match the TCAD mixed-mode circuit simulation results considerably well. Finally, we build and analyze ring oscillators using our M3INV to demonstrate the coupling impact on power and performance. [ABSTRACT FROM AUTHOR]

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation. [ABSTRACT FROM PUBLISHER]

This paper reviews the recent activities for normally-off GaN-based gate injection transistors (GITs) on Si substrates and their application to inverters. Epitaxial growth of the AlGaN/GaN heterostructures with good crystallinity over 200-mm Si substrates with eliminated bowing enables low-cost fabrication of GaN devices with high breakdown voltages. A novel normally-off GaN transistor called as GIT is proposed in which hole injection from the p-type AlGaN gate increases the drain current with low on-state resistance by conductivity modulation. The low on-state resistance in GaN-based devices greatly helps to increase the efficiency of power switching systems. A GaN-based three-phase inverter successfully drives a motor with high efficiency of 99.3% at a high output power of 1500 W. The presented GaN-based devices are expected to greatly help saving energy in the future as an indispensable power switching system. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power MOSFETs are available only for high-power and medium-to-high-voltage applications, generally above 600 V, because for lower blocking voltages, they comparatively provide lower advantages in terms of efficiency. There are applications, however, for which ruggedness and reliability are as important as efficiency, such as power optimizers for photovoltaic (PV) modules, which fall within the low power, low voltage category of dc–dc converters. These circuits, which maximize the energy produced by each single PV module, operate in continuously changing and stressing conditions yet having to assure high performances in terms of efficiency as well as of temperature insensitivity and long-term reliability. The aim of this paper is to predict the basic characteristics of a 4H-SiC MOSFET tailored for this kind of applications and, therefore, characterized by a breakdown voltage BVDS of 150 V and currents of the order of 10 A. The study, based on numerical simulations, shows that, besides the expected higher ruggedness, the static characteristics would be comparable to those of silicon MOSFETs rated for a comparable BVDS, with $R_{\mathrm{\scriptscriptstyle ON}}$ in the order of 100 $\text{k}\Omega {\cdot} \mu \text{m}^{2}$ , while advantages would result in terms of dynamic characteristics, and in particular in terms of switching times. [ABSTRACT FROM AUTHOR]

Due to its wide band gap, 4H-SiC is potentially capable of sustained operation at temperatures well above 600 ^\circ\C, but current devices are limited to lower temperatures by the stability of the metallization and passivation layers. SiC bipolar transistors are capable of operation at temperatures above 300 ^\circ\C, as they do not have an oxide layer under high electric field and hence do not suffer from oxide reliability issues. In this paper, we describe bipolar digital integrated circuits on semi-insulating 4H-SiC that operate over a wide range of supply voltage and temperature, demonstrating the potential of SiC for high-temperature small-scale integrated-circuit applications. [ABSTRACT FROM AUTHOR]

Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of band-to-band tunneling (BTBT) mechanisms into the compact model of a conventional carbon nanotube transistor FET featuring a MOSFET-like operation. Appropriate equations enable the calculation of the BTBT current as well as the charge pileup in the channel. To ensure the model accuracy and validate the equation set, the compact model simulation results are methodically compared with nonequilibrium Green function ones. Afterward, the investigations on the BTBT effects with respect to the figures of merits of the transistor and circuit have led to draw the conclusion that their impact is of utmost importance for large-signal analog and digital circuit designs. Neglecting the BTBT phenomena lead to an underestimation of more than 50% of the gate inverter delay and to an underestimation of power consumption of 30%. Finally, tradeoff recommendations between chirality and operating bias voltage are presented. [ABSTRACT FROM AUTHOR]

The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-κ gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-κ materials with permittivities > 30 can advantageously be used in CMOS technology, giving rise to further technological development. [ABSTRACT FROM AUTHOR]

Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film thickness. This study simulates a p-IMOS device on silicon-on-insulator using ATLAS. It is pointed out that the increase of the ratio LG/LIN allows a drop of the bias voltage, but involves a degradation of the subthreshold slope. A thin Si film improves the overall device performance. In the second part, the performance of an IMOS-based inverter is investigated, and for the first time an IMOS ring oscillator is simulated. [ABSTRACT FROM AUTHOR]

Organic complementary circuitry combines all the advantages of plastic electronics, such as flexibility, thinness, and solution processability with low power consumption. Here, we report organic complimentary inverters fabricated in a carrier-free batch process on a plastic foil with dielectric and semiconductor layers patterned using the high-volume gravure contact printing technique. The transistor components have bottom-gate, bottom-contact configuration with aluminum gates and gold contacts, allowing full use of photolithographic processing while protecting the semiconductors by depositing them last. Cross-linkable polymer dielectric, p-type small molecule and n-type polymer semiconductors are printed from inks based on nonchlorinated solvents. Printing instability is observed for capillary numbers approaching 1. The 430-nm-thick dielectric affords a relatively low operational voltage, and it is the thinnest printed organic dielectric reported in the literature for organic inverters to date. Both p- and n-type transistors have a mobility of 0.01–0.04 cm ^2\textV^\mathrm -1\texts^\mathrm -1 . The device parameters for the n-type transistors show less variation than the p-type transistors, which can be related to the more isotropic charge transport in polymer films compared with the small-molecule polycrystalline films. The resultant inverters have an average gain of 4.5 ± 1.5 and a maximum gain of 8 at V\mathrm {DD} =-20 V. The combination of the conventional photolithographic processing and gravure contact printing can therefore be used to fabricate bottom-gate organic complementary circuitry on plastic. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon nanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage ( \(V_{T}\) ). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher \(V_{T}\) . This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of \(\sim 0.5\) V between low- \(V_{T}\) and high- \(V_{T}\) configurations, while high- \(V_{T}\) configuration reduces the leakage current by two orders of magnitude as compared to low- \(V_{T}\) configuration. [ABSTRACT FROM AUTHOR]

We report on the fabrication of organic electrochemical transistors structured by nanoimprint lithography. The devices were scaled down as a result of our previous findings for inkjet printed transistors, where a reduced source-drain width and a shorter distance to the gate resulted in higher ON-to-OFF current ratios. We could show that these findings also prove true for transistors with feature sizes below 10 \mum . Furthermore, we fabricated inverters and NAND gates with switching times below 1 s. These logic gates mark an important step for organic electrochemical transistors toward their usability in more complex logic circuits. [ABSTRACT FROM PUBLISHER]

Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS hybridization, CMOS technology is essential for I/O, signal restoration, and maintaining compatibility with established technology. In spite of the SET's unparalleled advantages, its low current drive and output voltage when driving CMOS logic makes its use questionable in commercial ICs, specifically at the SET-CMOS interface. In this paper, we contribute to the design, analysis, and simulation of hybrid SET-CMOS circuits exploiting room-temperature operating SET technology. We developed an efficient computer-aided design tool to simulate large-scale SET and hybrid SET-CMOS circuits with conventional device elements. To demonstrate the SET logic driving capability for CMOS with interconnect parasitics, we analytically derived the SET logic parameters for the 22-nm technology node and used them to simulate hybrid SET-CMOS logic. We studied the performance of such hybrid logic circuit in terms of delay and bandwidth and addressed the tradeoffs between fabrication and electrical parameters. Our simulation results demonstrate the SET logic driving capability for CMOS comparable output voltage at gigahertz frequency in a hybrid SET-CMOS architecture. Finally, a comparison between SET and CMOS logic demonstrates that the SET logic outperforms CMOS. [ABSTRACT FROM AUTHOR]

Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in ION is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal–oxide–semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of ION, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts. [ABSTRACT FROM AUTHOR]

The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent to OTFT technology, these statistical variations are also taken into account. Finally, a circuit yield analysis is presented. [ABSTRACT FROM AUTHOR]

In this paper, we perform rigorous mixed-mode simulations on two-stage inverter circuit and sample-hold circuits, representative of digital, and analog applications, respectively. The impact of gate-source/drain overlap length on circuit performance in an 80-nm CMOS circuit is evaluated by varying the overlap length between 0 to 20 nm, while keeping the subthreshold leakage current constraint at 1, 10, and 100 nA/μm. Process variations about the nominal overlap length have also been accounted for. The stage delay and switch error are used as the performance metrics. The lateral peak electric field is used as the metric for the hot carrier it- liability. It is demonstrated that the overlap length should be made as small as possible, in spite of the increase in series resistance, in order to get the best circuit performance and reliability. [ABSTRACT FROM AUTHOR]

High-performance integrated tin monoxide bottom-gate staggered p-channel thin-film transistors (TFTs) are realized and reported. The active layer has been formed by thermal vacuum evaporation and rapid thermal annealing under a continuous nitrogen flow, resulting in field-effect mobilities up to 1.6 cm²/(V · s) and contact resistances of around 148Ω · cm. The integration of these TFTs in elementary building blocks for digital circuit applications such as inverters and ring-oscillators is demonstrated, resulting in stage delays down to 300 ns. Furthermore, a unipolar p-type-only 8-bit radio frequency identification code generator is realized, achieving 12.2 kb/s and comprising 294 tin monoxide TFTs. [ABSTRACT FROM AUTHOR]

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p+/n+ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage ( V D )-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration. [ABSTRACT FROM PUBLISHER]

We demonstrate low-temperature processed and high-gain unipolar inverters operating at voltages as low as VD = 1 V. A maximum gain for a two-transistor unipolar inverter of 153 was achieved at VD = 5 V with the advantage of using a solution-based n-type semiconductor and an entire fabrication process below 150 °C. We evaluate the impact of the gate dielectric thickness on the main thin-film transistor (TFT) parameters and operation voltage. In addition, we compare the conventional MOSFET square-law model indistinctly used in TFTs with a model specifically developed for TFTs. We demonstrate a methodology to model the TFT electrical characteristics and use the extracted parameters in SPICE simulations to evaluate different inverter configurations. Finally, we validate the SPICE simulations with our experiential results. [ABSTRACT FROM AUTHOR]

We present integrated inverter circuits based on junction FETs (JFETs) with ZnO channels and amorphous ZnCo2O4 gate contacts. The inverters reach high gain values up to 276 and uncertainty ranges down to 0.3 V for an operating voltage of 3 V. The magnitude of the gain is traced back theoretically to the slope of the JFET saturation current. The use of a level shifter is demonstrated, in order to obtain full inverters, which can be integrated into logic circuits. [ABSTRACT FROM PUBLISHER]

Organic complementary inverter is one of the key building blocks of some organic circuits, and the electrical performance and manufacture technique of inverter may determine its applications prospect. Through solution method, the organic complementary inverters were demonstrated based on triisopropylsilylethynyl-pentacene and N,N’-dioctyl-1,7-dicyano-perylene-(3,4:9,10)-tetracarboxylic diimide, which exhibited low operation voltage (4–10 V), high gain (12–27), large noise margin (>60% of 1/ 2V\mathrm {dd}) , low static power dissipation (tens of nanowatts), and a propagation delay time of $\sim 0.42$ ms. The solution processibility and overall performance of the inverter are highly promising for the applications in organic circuits. [ABSTRACT FROM PUBLISHER]

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high- \kappa /metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off-leakage variation (OLV), and operation voltage ( V_{\mathrm {DD}}) scaling limits of STI have been investigated. The typical SNM is 200 mV and the variability of the intermediate level ( \Delta V_{\mathrm {OM}}\sim 50 mV) from OLV can be allowable into the worst SNM (>100 mV) of STI operation at V\mathrm {DD}= 1 V. Exponentially reduced BTBT off-leakage around minimum V\mathrm {DD}\sim 0.1 V is promising for ultimate low-power application of our STI. [ABSTRACT FROM AUTHOR]

We found that field-effect mobility, which had been widely used in the evaluation of the mobility of an amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) failed to describe the effect of mobility on propagation delay ( tPD ) in an a-IGZO TFT-based circuit, and also proposed an extraction technique for the tPD -correlated mobility ( $\mu _{{{t_{\rm PD}}}}$ ) considering both the subgap density-of-states and the voltage-dependent charge density. It is verified that the proposed $\mu _{{{t_{\rm PD}}}}$ is the best correlated with the measured tPD in IGZO TFT-based inverters other than various mobilities in the literature. Our results have revealed that it is possible to predict tPD only with the measured current–voltage characteristic of the a-IGZO TFT without measuring tPD in IGZO-based circuits. [ABSTRACT FROM AUTHOR]

FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be attained. We report a new extension transistor-induced capacitance shielding (ETICS) phenomenon. In this phenomenon, the FinFET extension region forms a transistor, which shields gate-extension fringing field capacitance. Due to this phenomenon, we observe a strong dependence of effective values of FinFET logic gate capacitances on transition times of their terminal voltages, which is unlike the conventional transistors. We show that delay estimation methods need to be modified considering ETICS for efficient FinFET circuit design. [ABSTRACT FROM PUBLISHER]

A dual-gate thin-film transistor (TFT) has two gate electrodes. In inverted, staggered TFTs, the primary gate is usually the bottom gate (BG) and the TFT's threshold voltage (VTH) can be adjusted by applying a constant bias to the secondary gate, the top gate (TG), while scanning the BG. Dual-gate TFTs are being used as the load TFT in oxide semiconductor-based inverters, where the TG is biased positively to shift the VTH negatively and, thereby improving the inverter's output swing. Here, we show that the same can be achieved by the use of a floating TG. Furthermore, we show that the noise margin of the inverter can also be controlled by adding a biased TG to the driving TFT. [ABSTRACT FROM PUBLISHER]

High-performance pentacene-based thin-film transistors and inverters with solution-processed barium titanate (BTO) insulators are demonstrated. The current–voltage characteristics of the transistors show high mobility of 9.53 \cm^2\V^-1\s^-1 at smaller VG = -\3.5\ \V and VD = -\5\ \V, a low threshold voltage of -1.5 V, and a subthreshold slope of 599 mV/dec. Large grain and small crystalline sizes are observed from atomic force microscopy images and X-ray diffraction analysis of pentacene films. The results are verified through Raman spectroscopy and a theoretical Marcus–Hush equation to understand the higher intermolecular coupling, resulting in easier carrier transports in pentacene molecules. In order to investigate the behavior of high-permittivity materials of BTO insulators in a logic circuit, simple and low-operating-voltage inverters are fabricated, and the gain is approximately 8.76 under a small operating voltage range from 0 to -5 V. [ABSTRACT FROM PUBLISHER]

We present several fully printed organic complementary circuits using n- and p-type organic thin-film transistors. n-Type and p-type devices are developed on a flexible polyethylene-naphthalate substrate. All organic layers are deposited using a low-cost screen-printing technique. The inverters show a high gain and a switching point at exactly VDD/2. A seven-stage voltage-controlled oscillator (VCO) is designed with an organic output buffer, using the n- and p-type organic transistors. This VCO oscillates at a frequency of 186 Hz. Finally, two complementary differential amplifiers with high gain and large bandwidth are presented. The amplifiers only draw a 1-\mu\A current from a 40-V power supply. [ABSTRACT FROM AUTHOR]

A new drive method designed for the adaptive local dimming lighting of a multistructured 32-in diagonal-sized mercury-free flat fluorescent lamp (MFFL) which consists of a matrix array of 10 \times 16 60-mm diagonal-sized unit cells is proposed. The adoption of the dual auxiliary electrode and the bipolar-pulse drive scheme resulted in a wide stable operating voltage margin at low driving voltages. The cell turn-on or turn-off selectivity can be obtained through the change of the connection state of the dual electrode. Using the proposed MFFL with the dual auxiliary electrode as a data electrode and the subfield method, a new drive scheme for a 2-b adaptive local dimming control of 10 \times 16 lamp array with one inverter system is proposed and demonstrated. [ABSTRACT FROM PUBLISHER]

We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON-OFF ratios (104-106) while preserving the current drive. In addition, this metallic-nanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSI-compatible metallic-nanotube-tolerant design methodology. [ABSTRACT FROM AUTHOR]

The gate leakage current of HfO2 MOSFETs exhibits the power law characteristics after soft breakdown (BD) and the linear behavior after hard BD. Fast transient charge-trapping effect (FTCTE) shifts the inverter transfer characteristics but does not affect the high and low output voltages. The ring oscillator remains functional after gate BD. The BD position near the drain end of the n-channel transistor increases the noise figure (NF) significantly, whereas FTCTE has minor impact on the NF of the folded cascode low-noise amplifier. [ABSTRACT FROM AUTHOR]

In this brief, a new channel length modulation (CLM) extraction method is proposed. The main innovation of this approach is that the extracted value of CLM is not artificially inflated by the contribution of the drain-induced barrier lowering (DIBL), which allows discriminating between the two phenomena. In this method, the transistor gain is measured by using the source-measurement unit in a forced current mode. It is demonstrated that the CLM coefficient can be extracted by the linear regression of the inverse of the gain with respect to the current-over-transconductance ratio, corrected for series resistances. This method is later applied and validated on a planar bulk 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this brief, we investigate the electrical coupling between stacked field-effect transistors (FETs) in monolithic 3-D inverters (M3INVs). We study the range of interlayer dielectric (ILD) thickness ( T\text {ILD} ) and channel length Lg values that lead to a strong coupling between stacked FETs. Our device simulations show that M3INVs with T\text {ILD} \geq 50 nm lead to negligible interaction between the stacked FETs. In addition, our 3-D mixed-mode circuit simulations show that the switching threshold voltages, propagation delays, and fall times of M3INVs with T\text {ILD} < 50 nm are significantly affected by other tiers. This means that new circuit simulation techniques that consider the electrical coupling between the stacked devices are required in monolithic 3-D integrated circuits. [ABSTRACT FROM PUBLISHER]

This brief presents a low-power high-stability scan driver integrated by In–Zn–O (IZO) TFTs on polyimide substrate. Observed from the experimental results of the scan driver with 48 stages, there is no distortion and good noise-suppressed characteristics for the output waveforms. In one stage of the proposed scan driver, there only needs a small TFT connected to clock signals by using a feedback inverter and a dc output module to minimize the dynamic power consumption. It is measured that the power consumption for one stage of the proposed gate driver is 18.3 \mu \textW at the output swing of 15.3 V and the clock frequency of 50 kHz. There is a good noise-suppressed characteristic and high stability for the proposed scan driver as shown from a 300-h test. [ABSTRACT FROM AUTHOR]