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In the first part of this article, a physics-based surface-potential compact model to describe current–voltage (I–V) relationship in few-layered ambipolar black phosphorus (BP) transistors is presented. The proposed model captures the essential physics of thin-film BP FETs by accounting for the effects of: 1) in-plane band-structure anisotropy in BP, as well as the asymmetry in electron and hole current conduction characteristics; 2) nonlinear Schottky-type source/drain contact resistances; 3) interface traps; 4) ambipolar current conduction in the device using two separate quasi-Fermi levels for electrons and holes; and 5) the effect of temperature on the model parameters. In this article, the model is validated against measured data of back-gated BP transistors with gate lengths of 1000 and 300 nm with the BP thickness of 7.3 and 8.1 nm and for the temperature range of 200–298 K. We also validate the model against numerical TCAD data of BP transistors with channel lengths of 300 and 600 nm and BP thickness of 6 nm. The model is also applied to unipolar 2-D FETs with channel materials, such as MoS2 and WSe2. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here shows excellent agreement with experimental and numerical data over broad bias and temperature range. [ABSTRACT FROM AUTHOR]

We report a physics-based surface-potential compact model to describe current–voltage (I – V) relationship in a few-layered ambipolar black phosphorus (BP) transistors. To model the device electrostatics, the 2-D density of states of carriers and Fermi–Dirac statistics are used, while carrier transport is described using the drift-diffusion formalism. The model also comprehends the effects of interface traps and voltage-dependent Schottky-type source/drain contact resistances. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here is applicable over broad bias and temperature range. Validation of the model against measurement data of BP transistors with gate lengths 300–1000 nm and operating temperature from 200–298 K is demonstrated in a companion article. [ABSTRACT FROM AUTHOR]

Precise measurements of the mobility anisotropy along high-symmetry crystal axes in black phosphorus (BP) MOSFETs are reported. Locally back-gated BP MOSFETs with 13-nm HfO2 dielectric and channel length ranging from 0.3 to 0.7 $\mu \text{m}$ are fabricated. A single BP flake of a uniform thickness is exfoliated and etched along armchair (AC) and zigzag (ZZ) crystal axes, and the orientations are confirmed using optical and transmission electron microscopy analyses. The hole and electron mobilities along each direction are extracted using the transfer length method. The AC-to-ZZ hole mobility ratio is found to increase from 1.4 (1.5) to 2.0 (2.9) as the sheet concentration increased from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 at room temperature (77 K). The room-temperature electron mobility anisotropy is found to be similar to that for holes with an AC-to-ZZ mobility ratio increasing from 1.4 to 2.1 from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 though electrons showed only a very weak temperature dependence. A Boltzmann transport model is used to explain the concentration- and temperature-dependent mobility anisotropies which can be well described using a charge center scattering model. [ABSTRACT FROM AUTHOR]