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We report a physics-based surface-potential compact model to describe current–voltage (I – V) relationship in a few-layered ambipolar black phosphorus (BP) transistors. To model the device electrostatics, the 2-D density of states of carriers and Fermi–Dirac statistics are used, while carrier transport is described using the drift-diffusion formalism. The model also comprehends the effects of interface traps and voltage-dependent Schottky-type source/drain contact resistances. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here is applicable over broad bias and temperature range. Validation of the model against measurement data of BP transistors with gate lengths 300–1000 nm and operating temperature from 200–298 K is demonstrated in a companion article. [ABSTRACT FROM AUTHOR]

Precise measurements of the mobility anisotropy along high-symmetry crystal axes in black phosphorus (BP) MOSFETs are reported. Locally back-gated BP MOSFETs with 13-nm HfO2 dielectric and channel length ranging from 0.3 to 0.7 $\mu \text{m}$ are fabricated. A single BP flake of a uniform thickness is exfoliated and etched along armchair (AC) and zigzag (ZZ) crystal axes, and the orientations are confirmed using optical and transmission electron microscopy analyses. The hole and electron mobilities along each direction are extracted using the transfer length method. The AC-to-ZZ hole mobility ratio is found to increase from 1.4 (1.5) to 2.0 (2.9) as the sheet concentration increased from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 at room temperature (77 K). The room-temperature electron mobility anisotropy is found to be similar to that for holes with an AC-to-ZZ mobility ratio increasing from 1.4 to 2.1 from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 though electrons showed only a very weak temperature dependence. A Boltzmann transport model is used to explain the concentration- and temperature-dependent mobility anisotropies which can be well described using a charge center scattering model. [ABSTRACT FROM AUTHOR]

We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 \nA/\mu\m and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal–oxide–semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits. [ABSTRACT FROM PUBLISHER]