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We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 \nA/\mu\m and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal–oxide–semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits. [ABSTRACT FROM PUBLISHER]

We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ∼8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed OFF-state current of 100 nA/µm and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field). [ABSTRACT FROM AUTHOR]

N-and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates. [ABSTRACT FROM AUTHOR]