Search

Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ($\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%. [ABSTRACT FROM AUTHOR]

Efficiency roll-off defined as the rapid efficiency drop by increasing the electrical current density is a major issue in the design of novel organic light-emitting diodes (OLEDs) based on thermally activated delayed fluorescence (TADF). In this paper, it is shown that efficiency enhancement and suppression of efficiency roll-off in TADF OLEDs can be accomplished by broadening the exciton generation zone by precisely tuning the doping concentration of the TADF emissive material in the host matrix. This universal and simply tunable parameter can be applied to any TADF OLED to further enhance its performance characteristics. In this paper, a typical TADF OLED with realistic parameters is numerically investigated by solving the charge carrier transport and excitonic equations and taking into account all relevant processes such as triplet–triplet annihilation, triplet–polaron, and singlet–triplet quenching, and (reverse) intersystem crossing. It is shown that the internal quantum efficiency (IQE) decreases at very low and very high doping densities due to exciton distribution nonuniformity and charge balance factor reduction, respectively. Power efficiency depends on the IQE as well as the potential drop across the emissive layer and decreases at very low doping densities even for a perfectly balanced device; however, the reduction for an unbalanced device is much more substantial. For a perfectly balanced device with an emissive layer thickness of 30 nm, at a current density of 10 mAcm−2, the IQE can be increased from 18% to more than 58% by decreasing the doping concentration from ${c}= {15}$ % to 0.5%. Power efficiency reaches its peak value of 38 lm/W at 1.4% doping. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

Nowadays, the importance of the blood particles separation is undeniable in medical fields and there are different sorts of separation methods accordingly. Acoustic cell separation is chosen in this paper. Also, numerical methods have been used to study the effect of geometrical factors on the separation of the particles before spending time and expenses in a trial and error manner experimentally. We have implemented a plenary finite-element-based simulation of separating blood particles such as white blood cells and platelets in an acoustic field using standing surface acoustic waves. In this paper, unlike previous works in which the channel is rectangular; the channel is trapezoidal in order to make the separation more efficient. By changing the trapezoidal leg angle, WBC’s distance from the midline will be different. The designed device is a bio-MEMS channel containing two inlets which are for the sheath flow and for the blood particles, a trapezoidal main channel, and three outlets. Two aluminum interdigital transducers are located on the LiNbO3 substrate. For creating the acoustic force, we have applied an alternating voltage to transducers. Blood particles will be moved toward the acoustic nodes because of the positive acoustic contrast factor. Since acoustic radiation force depends on the size of the particles and their compressibility, cells can be sorted according to their diameter and compressibility; hence, particles will be separated. For optimizing the device, we have changed the trapezoidal channel angle, the input voltage, and the flow rate. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

Recent studies of electroluminescent cooling (ELC) in III–V structures demonstrate the need to better understand the factors affecting the efficiency of light emission and energy transport in light-emitting diodes (LEDs). In this paper, we establish the physical and operational requirements for reaching the efficiencies needed for observing ELC in the III–V intracavity double-diode structures at high powers. The experimentally validated modeling framework used in this paper, coupling the drift-diffusion charge transport model with a photon transport model, indicates that the bulk properties of the III–V materials are already sufficient for ELC. Furthermore, the results suggest that the bulk power conversion efficiency of the LED in the devices, which allowed the experimentally measured record high coupling quantum efficiency of 70%, already exceeds 115%. However, as shown here, direct observation of ELC by electrical measurements still requires a combination of a more efficient suppression of the nonradiative surface recombination at the LED walls and the reduction of the detection losses in the photodetector of the intracavity structures. [ABSTRACT FROM AUTHOR]

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length. [ABSTRACT FROM AUTHOR]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

In this paper, we examine the interplay of two serious reliability issues in MOSFET devices, namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most publications are devoted to the characterization of either BTI or HCD, and complex models have been developed to independently describe each degradation mode. However, very limited data are available on the interplay of both degradation regimes, particularly the effect of a drain bias onto the charging and discharging dynamics of oxide traps. Part I of this paper provides an extensive experimental study toward the impact of mixed-mode stress conditions on the dynamics of oxide defects. Here, we present the first microscopic modeling approach beyond a simple electrostatic approximation. We extend the existing nonradiative multiphonon theory by taking nonequilibrium processes such as full carrier distribution functions which include the effect impact ionization along the channel into account. To ultimately validate our framework, we compare simulation results and experimental data for a single-oxide defect as well as a large ensemble of traps in a MOSFET device. We show that our modeling approach accurately captures the rather puzzling measurement trends for a broad stress regime and allows developing the knowledge on how oxide defects can be affected by an increased drain stress. [ABSTRACT FROM AUTHOR]

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

This paper presents a new method for modeling the nonideal conductance response (CR) of synaptic devices. Unlike previous studies, which utilize physical device properties for modeling, this paper only uses the measured CR data. This allows the proposed modeling method to be easily applied to various types of synaptic devices without considering the unique physical properties of each device. An efficient piecewise linear approximation method which offers a tradeoff between computational complexity and simulation accuracy of neural networks is also presented to generate a linear device model out of nonlinear CR data. In addition, model parameters, which reflect the nonideal characteristics of the CR such as abrupt and asymmetric conductance changes, conductance variation, and limited conductance dynamic range, are introduced to evaluate the network performances in the presence of the nonidealities. By adjusting the model parameters, the desired CR satisfying the network performance requirements can be derived for device development. A three-layer neural network employing the device model has been designed and trained for the MNIST data set in order to demonstrate the application of the model to system-level simulations and verify the effectiveness of the modeling method. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly. [ABSTRACT FROM AUTHOR]

This paper investigates the impacts of typical semiconductor material properties—electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core–shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core–shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications. [ABSTRACT FROM PUBLISHER]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

In this paper, we present the operation principle of an organic metal–insulator–semiconductor (MIS) capacitor where the organic semiconductor is undoped. In spite of a low charge concentration within the semiconductor, this device exhibits a capacitance variation with respect to the applied gate voltage yielding the capacitance–voltage characteristics similar to that of a traditional MIS capacitor based on the doped semiconductor. A physics-based model is developed to derive the charge concentration, surface potential, and the capacitance of the organic MIS capacitor. The model is validated with TCAD simulation results as well as with experimental data obtained from the fabricated organic MIS capacitor consisting of poly(4-vinylphenol) and poly(3-hexylthiophene-2, 5-diyl) as an insulator and a semiconductor, respectively. [ABSTRACT FROM AUTHOR]

A partially dielectric-loaded (PDL) nonuniform grating with lower ohmic losses for a sheet beam backward wave oscillator (BWO) and a clinotron is proposed in this paper. The expressions of the electromagnetic fields for the PDL nonuniform-grating-based slow-wave structure (SWS) are derived by using Maxwell’s equations and Floquet’s theorem. The dispersion equation is derived using the field-matching method and is verified by simulation. The expression of the Pierce small signal gain of a BWO with a PDL nonuniform grating is obtained by using the electromagnetic field expressions and the small signal gain theory. The effects of different parameters on the gain of a BWO with a nondielectric-loaded (NDL) nonuniform grating and those of a BWO with a PDL nonuniform grating are discussed, and the mode competition of this kind of BWO is analyzed in terms of gain. The oscillation frequencies obtained from the mode competition analysis are verified by a particle-in-cell (PIC) simulation, confirming the validity of the analysis. [ABSTRACT FROM AUTHOR]

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field-effect transistors. Our potential model takes into account the charge carriers in the channel, as well as the space charges in the depletion regions of the two reservoirs. Later, this potential model is utilized to calculate the band-to-band tunneling generation rates at any spatial coordinate in the tunneling volume. Next, these rates are integrated over tunneling volume to find the total tunneling current. This leads to an analytical model for the drain current. We validate our models against the data obtained via numerical simulations for several common heterojunction tunnel devices at various geometries and bias conditions. [ABSTRACT FROM AUTHOR]

A physics-based threshold voltage model of junction-less (JL) double gate (DG) FETs with vertical structural and doping asymmetry is being proposed in this paper. The numerical implementation of vertical asymmetric doping in the FET devices modeling has been studied extensively. A linear approximation, as suggested in the post-annealed implantation technique, is introduced to account for asymmetric-doped profile falling within the channel thickness. Furthermore, Bhaskar’s approximation of sinusoidal has been implemented in the solution to impart due accuracy in the modeling overextended range of device parameters. Overall, appropriate implementation of these mathematical techniques has reduced the complexity of the full evanescent mode analysis immensely and has together retained the accuracy in the solution. The simplicity of the model has provided flexibility to study structural and doping asymmetry together for JL DG FET. Synopsys Sentaurus Device simulation tool has been used for verification of the model results. [ABSTRACT FROM AUTHOR]

More and more attention has been paid to the heterogeneous semiconductor device based on the wafer-bonding method due to its high-quality wafer-bonded active layer. In this paper, we first theoretically study the dependence of the single-photon properties, including the single-photon detection efficiency (SPDE), dark count rate (DCR), and afterpulsing probability (AP), of the wafer-bonded Ge/Si single-photon avalanche photodiode (SPAD) on the interface state at the Ge/Si (hydrophilic reaction) and Si-Si (hydrophobic reaction or surface-activated method) wafer-bonded interface based on the Poisson statistics. It is found that the interface state density and the energy level position of the interface state significantly affect the linear-mode electric field distribution (avalanche probability), 3-dB bandwidth (dark carriers), gain (quantum efficiency), and effective transit time (trapped carriers), which in turn affect the DCR and the SPDE. Furthermore, the dependence of the AP on the avalanche charge and the interface recombination rate is clarified as well. It is expected that this paper may give guidance for the fabrication of high-performance SPAD. [ABSTRACT FROM PUBLISHER]

In this paper, a novel design for the emission layer of the fluorescent organic light-emitting devices is presented to suppress the efficiency roll-off and maintain the high efficiency at both low and high current regimes. In the emission layer, the emitter material is blended with a manager or host material with proper charge carrier transporting and excitonic energy levels. The charge carriers and excitons undergo a carefully designed route in this manager–emitter blend so that the triplet excitons always contribute positively to the efficiency through triplety–triplet annihilation (TTA), and the competing mechanisms are severely weakened. The required characteristics of the emitter and host materials for the proper functioning of the proposed strategy are completely discussed in this paper. The proposed scheme is verified through detailed numerical simulations, and it is shown that the efficiency roll-off can be effectively suppressed. The overall efficiency depends on the TTA yield in producing singlet excitons. For the yield of 0.5, an internal quantum efficiency of 50% at the current density of 10 mAcm ^-2 is computed, which increases as the triplet density increases reaching the value of 58% at the current density of 1 Acm ^-2 . [ABSTRACT FROM PUBLISHER]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

In this paper, we systematically evaluate the variation in the reversal delay of a nanomagnet driven by a longitudinal spin current under the influence of thermal noise. We then use the results to evaluate the performance of an all-spin-logic (ASL) circuit. First, we review and expand on the physics of previously published analytical models on stochastic nanomagnet switching. The limits of previously established models are defined, and it is shown that these models are valid for nanomagnet reversal times <200 ps. Second, the insight obtained from previous models allows us to represent the probability density function (pdf) of the nanomagnet switching delay using the double exponential function of the Fréchet distribution. The pdf of a single nanomagnet is extended to more complex nanomagnet circuit configurations. It is shown that the delay-variation penalty incurred by nanomagnets arranged in parallel configuration is dwarfed by the average delay increase for nanomagnets arranged in a series configuration. Finally, we demonstrate the impact of device-level performance variation on the circuit behavior using ASL logic gates. While the analysis presented in this paper uses an ASL-AND gate as the prototype switching circuit in the spin domain, the physical concepts are generic and can be extended to any complex spin-based circuit. [ABSTRACT FROM PUBLISHER]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel generalized multiparticle drift-diffusion (mp-DD) model capable to overcome some limitations imposed by the classic drift-diffusion model by taking into account multiple carrier populations. We demonstrate the model’s ability and flexibility in simulating systems from different application contexts. We conclude that the developed mp-DD model allows investigating a wide range of complex mechanisms, such as subband charge transport calculation or intersystem crossing (ISC), which are crucial for the understanding and design of organic and inorganic semiconductor devices largely employed for both photovoltaics and light emitting applications. [ABSTRACT FROM AUTHOR]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

The nonlinearity characteristics of memristor have been widely employed in artificial intelligence. However, existing studies do not provide much attention to the analytic analysis of nonlinearity. This paper presents an analytic approach to the nonlinearity of memristor by analyzing the output spectrum based on homotopy analysis method (HAM). The analytic spectrum expressions obtained by this approach are verified by the fingerprints of memristor. It can be simultaneously revealed that one of the potential sources of the nonlinearity is the large variation of state variable. Furthermore, we propose a mapping method based on the obtained total harmonic distortion (THD) and a new parameter—threshold frequency $\omega _{C}$ to investigate the relationship between the memristor transition (i.e., the transition of the memristor between a nonlinear resistor and a linear resistor) and the frequency of input signal. Especially, analytic output spectrum, THD, and threshold frequency $\omega _{C}$ can be solved without complex mathematical operations and, thus, compared with traditional works, the complexity of the proposed approach is reduced. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

In this paper, we target the compact capacitance modeling of organic thin-film transistor (OTFTs) valid from depletion to accumulation regime taking into account the frequency dependence. The parameters used in the model are calculated through the unified model and parameter extraction method (UMEM). We include the effect related to the density of localizated states in the gate capacitance. Finally, we analyze the experimental derivative of the gate capacitance, and we demonstrate that our model predicts it with a high degree of accuracy. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

Modeling of the packaged wind sensor operating on constant power (CP) mode is proposed in this paper. The proposed model is based on the theory of heat conduction and forced convection. The presented model indicates that the total output dc voltage is proportional to the square root of the wind speed, and ${V}_{x}$ , as well as ${V}_{y}$ , varies with the wind direction based on cosine function. The wind sensor is fabricated by microelectromechanical systems (MEMS) technology and packaged with the glue. The test is performed in the wind tunnel and the measured results indicate an agreement with the presented model. The relative error of voltage for the wind speed is less than 14% up to 30 m/s, while that for the wind direction is no more than 10.7% from 0° to 360°. [ABSTRACT FROM AUTHOR]

As is well known, a roadblock to realizing the full potential of GaN high-electron mobility transistors (HEMTs) for power amplifier applications is the peaked nature of the transconductance and the resulting power-gain roll-off exhibited by these devices. Motivated by promising work on compositionally graded HEMT designs, in this paper we explore this design solution using the numerical device simulation. Among other things, we examine the consequences of saturation velocity, grading profile, alloy scattering, and device scaling. In addition, lumped element modeling of the large-signal behavior is carried out to assess the power amplifier performance. We also compare the graded approach with another known method of linearity improvement in which the source resistance is reduced. In general, we find much to recommend in the graded-channel approach, especially for gate lengths greater than about 100 nm. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

Hexagonal boron nitride encapsulation significantly improves carrier transport in graphene. This paper investigates the benefit of implementing the encapsulation technique in graphene field-effect transistors (GFETs) in terms of their intrinsic radio frequency (RF) performance, adding the effect of the series resistances at the terminals. For such a purpose, a drift-diffusion self-consistent simulator is prepared to get the GFET electrical characteristics. Both the mobility and saturation velocity are obtained by an ensemble Monte Carlo simulator upon considering the relevant scattering mechanisms that affect carrier transport. RF figures of merit are simulated using an accurate small-signal model. Results reveal that the cutoff frequency could scale up to the physical limit given by the inverse of the transit time. Projected maximum oscillation frequencies, in the order of few terahertz, are expected to exceed the values demonstrated by InP and Si-based RF transistors. The existing tradeoff between power gain and stability and the role played by the gate resistance are also studied. High power gain and stability are feasible even if the device is operated far away from current saturation. Finally, the benefits of device unilateralization and the exploitation of the negative differential resistance region to get negative-resistance gain are discussed. [ABSTRACT FROM AUTHOR]

In this paper, a 3-D fast time-domain nonlinear algorithm (FTDNA-3-D) based on particle-in-cell method for the beam–wave interaction of the sheet beam slow wave structure (SWS) is presented. Calculation equations of the circuit electric field and the space charge electric field are given. Calculation approaches of the energy exchange and the particle mover are displayed. A simplified coupling impedance simulation approach for sheet beam SWS is indicated. The FTDNA-3-D takes the transverse electric field and the focusing magnetic field into consideration. The FTDNA-3-D could reach a high simulation speed. This novel algorithm gives a faster accurate choice for the design of sheet beam traveling-wave tube (TWT). It could be used to enhance the design efficiency of sheet beam TWT. A Ka-band staggered double vane TWT is used to verify the FTDNA-3-D. Simulation results of output power and gain versus frequency from FTDNA-3-D are compared with results from CST particle studio. The results of FTDNA-3-D are in accord with CST particle studio well. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]