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The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model. [ABSTRACT FROM AUTHOR]

In this paper, we have investigated the leakage current versus voltage characteristic of high- k thin film capacitors over a large temperature range. Fabricated samples, consisting of a 10-nm thin {\rm SrTiO}_{3} (STO) layer as a dielectric material and {\rm SrRuO}_{3}$ as electrodes, have been examined. Electrical measurements performed at different temperatures reveal leakage currents that exceed 10^{-7}~{\rm A}/{\rm cm}^{2} at 1 V, a requirement needed for dynamic random access memory (DRAM) applications. We perform a detailed simulation study for the measured samples, making use of a modified drift diffusion model, which also takes into account charge trapping/detrapping effects and nonlocal tunneling. Based on our simulations, we propose an explanation for the large leakage currents observed experimentally. They can be attributed to a trap-assisted tunneling process that is enhanced by oxygen vacancies in the STO dielectric layer. We are thus able to reproduce the temperature and voltage dependence of the measured currents and can use our model to examine the impact of different physical parameters on the behavior of the capacitor structure—a first step toward device optimization. A feasibility analysis is performed for a 1T1C DRAM cell using an optimized deep trench STO capacitor with a reduced oxygen defect density. The simulation results underline the advantages of our modeling procedure using a commercial technology computer aided design (TCAD) framework: once the complex leakage mechanism is implemented, it can be activated on arbitrary 3-D structures, taking advantage of all the postprocessing or visualization capabilities. [ABSTRACT FROM AUTHOR]