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Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

Spin transfer torque (STT)-based switching of magnetic random access memories (MRAMs) has stimulated considerable research interest in recent years. The nonvolatility of STT-MRAMs, high areal density, and low static power dissipation makes them a strong contender for possible replacement of conventional silicon-based memories. However, a major bottleneck associated with STT-MRAMs is their high write current requirement. Recently, it has been demonstrated that the high write current of the STT switching mechanism can be improved by using other magnetic switching techniques like voltage-controlled magnetic anisotropy, spin Hall effect, and magnetoelectric effect. Interestingly, each of these new physics increases the design space to be explored and presents interesting tradeoffs with respect to read and write mechanisms. It is, therefore, important to analyze these devices with respect to their readability, writability, and areal density in a unified framework that is based on the state-of-the-art experimental results. Toward that end, in this paper, we present an overview of various physics underlying these magnetic memories and discuss associated bit-cell circuitry. Furthermore, we present a holistic comparative analysis based on detailed numerical simulations highlighting the various design tradeoffs. [ABSTRACT FROM AUTHOR]