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A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]