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In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

Selector-less resistive random-access memory (RRAM) devices require high nonlinearity (NL) in low-resistance state current ( ${I}_{\textsf {LRS}}$ ). In this paper, we investigate the effect of composition (here, Ca%)-dependent material properties, viz., ion migration barrier, and thermal conductivity, on memory performance of recently demonstrated Pr1–xCaxMnO3-based selector-less RRAM with high NL. First, the NL increases as “ $\mathit {x}$ ” decreases. This is attributed to higher self-heating in $\textsf {PCMO}{(}\mathit {x}{)}$ films as composition-dependent thermal conductivity ( $\kappa $ ) decreases as “ $\mathit {x}$ ” is decreased. This enables selector-less operation. Second, larger memory window is observed as “ $\mathit {x}$ ” increases due to decrease in the voltage required for onset of RESET process (i.e., $V_{\textsf {MIN, RESET}}$ ) as “ $\mathit {x}$ ” is increased. Lower $V_{\textsf {MIN, RESET}}$ at higher “ $\mathit {x}$ ” is due to higher oxygen-ion conductivity attributed to lower migration barrier ( ${E}_{m}$ ). Third, retention is measured at different temperatures to extract composition-dependent ${E}_{m}$. The poor memory retention performance for $\mathit {x}= 1$ is consistent with lower ${E}_{m}$ estimated. Finally, enhanced endurance is observed for lower ${E}_{m}$ due to low-energy requirement for switching. Based on these observations, an interrelation between ${E}_{m}$ , retention, and endurance is established. Therefore, an interplay of composition-dependent thermal conductivity and oxygen-ion migration barrier enables tunable memory characteristics in Pr1–xCaxMnO3-based RRAM. [ABSTRACT FROM AUTHOR]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

In this paper, the presence of filamentary current instabilities in the high resistance state of Ni/HfO2-based RRAM devices and their associated current fluctuations mechanisms are explored. After systematic measurements, the advanced weighted time-lag plot method is employed to accurately identify the contribution of multiple electrically active defects and to minimize the negative effect of the background noise. Special attention is given to the physical analysis of multilevel random telegraph noise (RTN) signals caused by both independent and interactive defects located in the vicinity of the conductive filament (CF), which may alter the tunneling path and induce large stochastic current fluctuations. In addition, irreversible current changes, owing to trap density variations inside or near the CF, are also identified. Finally, the voltage dependence of the RTN phenomena and the occurrence of stress-induced complex fluctuations is evaluated. [ABSTRACT FROM PUBLISHER]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

In this paper, the resistive switching behavior of a single-component-polymer resistive memory device based on polychloro-para-xylylene (parylene-C) is comprehensively studied. With the excellent chemical stability and high process compatibility of parylene-C, an 8 \times 8 crossbar array with a sandwiched structure of parylene-C and active electrodes is fabricated, which can be integrated in the CMOS back-end process and shows great potentials for future transparent, low-cost, flexible, and high-density nonvolatile memory applications. This organic memory device exhibits excellent performance with a \10^7 on/ off current ratio, nanosecond set/reset speed, and low switching voltages, as well as good retention and cycling endurance behaviors. The switching mechanism is systematically investigated with the comparison between active electrodes (Al, Cu, or Ag) and an inert electrode (Pt), as well as the dependence on temperature and device area. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

This paper reports the effects of rapid thermal annealing (RTA) on resistive switching (RS) characteristics and mechanisms of \SrZrO3 (SZO)-based memory devices. SZO thin films were deposited on \LaNiO3 (LNO) (\100)/\Pt/Ti/SiO2/\Si using radio-frequency magnetron sputtering and were followed by an RTA process in \N2, Ar, and \O2 ambients, respectively, at various temperatures for improving RS performance. Experimental results indicate that an SZO device annealed in \O2 at 600 ^\circ\C (\O2-600) exhibits stable RS properties and has a high device yield (\sim 90%), a reliable retention characteristic (up to \1 \times \10^6\ \s at 100 ^\circ\C), and steady nondestructive readout properties (over \1.4 \times \10^4\ \s at 100 ^\circ\C). However, by increasing RTA temperature to more than 700 ^\circ\C, random formation of LNO (110) precipitates on the bottom surface of SZO grains might shorten the effective thickness of the SZO thin films. Furthermore, a strong electric field possibly occurs at the region between Al top electrodes and low-resistivity LNO precipitates. It is speculated that an RS phenomenon, which occurs within SZO grains instead of on grain boundaries, easily leads to RS failure, further resulting in severe degradation of device yield in the \O2-700 and \O2-800 devices. When compared with other devices, \O2-600 SZO memory devices exhibit highly reliable RS characteristics. [ABSTRACT FROM AUTHOR]