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The proposition of integrating the 2-D materials and ferroelectric negative-capacitance MOSFETs (NCFETs) was expected to have excellent steep slope I – V characteristics due to the combined advantages of both ultrathin body channel material and negative-capacitance effect. Recent experiments demonstrated the excellent steep slope features of 2-D material NCFETs. Therefore, it was important to understand the device physics of this characteristic, its performance projection, and the benchmark with NCFETs based on conventional Group IV materials. In this article, we conducted a computational study of 2-D material NCFETs based on MoS2 under the nonequilibrium Green’s function (NEGF)-Poisson self-consistent scheme with free-Gibbs energy calculation to judge the operating path in polarization–electric field (P–E) relation. Monolayer MoS2 (1L-MoS2) was chosen as channel material while various thickness of ultrathin body silicon (UTB-Si) for benchmark purpose. The results showed an excellent average subthreshold slope (SS) of ~25 mV/dec in 1L-MoS2 NCFETs compared to ~32 mV/dec of the UTB-Si counterparts. It was found that the steep-slope features in 1L-MoS2 NCFETs could be attributed to the more optimized capacitance matching in 1L-MoS2 NCFETs and tunneling currents at the subthreshold region. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) negative capacitance (NC) MOSFETs is investigated in depth with a full real-space atomic simulator. For the first time, Gibbs-free energy of the whole atomic system is employed to determine the appropriate operation region in polarization-electric-field (${P}$ – ${E}$) path of the FE layer for FE MOSFETs. With different FE thicknesses, the operation path of the FE layer in MOS structures can be hysteresis or hysteresis-free. For MOSFET structures, the operation path of FE layer will vary with different FE materials. With proper device parameters, the NC effect in FE layer can be obtained with minimum Gibbs-free energy of the MOS and MOSFET structures. The body factor, ${dV}_{G}/{d} \Psi _{S}$ , is obtained with the real-space structure to reflect the influence of the FE layer and optimize the device performance. With the FE layer of the same thickness, the NC-FET with longer channel has a larger body factor which causes the tradeoff between low tunneling current and small body factor. This tradeoff makes it difficult to improve the subthreshold swing by changing the gate length. In addition, the effect of floating metal layer between FE and SiO2 layers in NC-FETs is studied in detail with atomic level real-space analysis for different gate lengths. The metal layer has a stronger influence on the electric characteristics of NC-FETs with longer channel. [ABSTRACT FROM AUTHOR]

We report the ultimate performance of a double-gate ultrathin body (DG-UTB) FET employing materials from group IV, III-V, and 2-D materials based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high-performance (HP) and low-power (LP) technologies. The band structures of the channel materials were obtained using the sp ^3\textd^5\texts^\ast tight binding model and the first-principles density functional theory. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The leakage current due to direct source-to-drain tunneling was calculated based on Wentzel–Kramers–Brillouin approximation. For nFET used in the HP technology, GaSb nFET has the best voltage scalability followed by Ge nFET in 2026. It was found that I\mathrm{\scriptscriptstyle ON} of InAs and In0.3 Ga0.7Sb nFETs is among the lowest, and they require larger power supply voltage ( V\mathrm{DD} ) among III-V semiconductors considered to achieve I\mathrm{\scriptscriptstyle ON} of silicon nFET. However, they show lower power delay product (PDP) due to their smaller electron effective mass, resulting in higher carrier velocity. Ge pFET offers the best voltage scalability for pFET used in the HP technology. For the voltage scalability assessment based on the requirements for the LP technology, MOSFETs based on Si offer better performance in terms of I\mathrm{\scriptscriptstyle ON} and PDP than MOSFETs based on 2-D materials. Among the 2-D materials studied, black phosphorus and silicane MOSFETs exhibit higher I\mathrm{\scriptscriptstyle ON} and better voltage scalability and PDP. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

Silicon CMOS technology has fueled the phenomenal growth in semiconductor electronics over the past several decades. The miniaturization of a transistor, the basic tenet of technology scaling, is at the core of this revolution. Despite several challenges, the innovations in materials, processes, and device architecture have ensured that Moore’s law is still alive and going strong, with 7-nm silicon FinFET technology in volume production. However, over the past couple of decades, there has been a realization that the silicon CMOS technology may reach the end of scaling unless it is augmented and complemented by other semiconductors. For instance, there has been a substantial effort in the research community to integrate other bulk semiconductors such as germanium and III-Vs, into silicon technology. [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]

Black phosphorus (BP) has been proposed as the channel material in the next generation ultrascaled CMOS devices. In order to gain insight into the current characteristics in 2-D layered materials, the current distribution of a few-layer BP Schottky barrier FET is investigated via state-of-the-art quantum device simulations. Approximately 40% of the total current was found to be concentrated in the top layer when the device was switched on, with the remaining current distributed among the other layers. In comparison, ~80% of the current concentrated below the surface in a Si device with the same structure. These features are related to the strength of the intra/interlayer interaction in few-layer BP and are unique to 2-D layered materials. Moreover, the current distribution and the device performance were different for the top- and side-contacted devices, with the side-contacted devices yielding lower resistance compared with the top-contacted devices. [ABSTRACT FROM PUBLISHER]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length ( $L_{{\mathrm{CH}}}$ ), NW height ( $H_{{\mathrm{NW}}}$ ), and NW width ( $W_{{\mathrm{NW}}}$ ) were realized. Despite having a large equivalent oxide thickness of $\sim 4.5$ nm, high extrinsic transconductance ( $G_{{m,{\mathrm{ ext}}}}) of 820 \mu \textS/\mu \textm was achieved at V\mathrm{ D} of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance ( R\mathrm {SD} ) of 275 \Omega \cdot \mu \mathrm m , which is one of the lowest among the reported 3-D InGaAs MOSFETs. [ABSTRACT FROM PUBLISHER]

We investigated the effect of body thickness on the electrical performance of GaSb double-gate ultrathin-body (DG-UTB) MOSFET by examining the band structure of the 12- ( $\sim 2$ nm), 24- ( $\sim 4$ nm), 36- ( $\sim 6$ nm), and 48- ( $\sim 8$ nm) atomic-layer (AL) thick GaSb. Two different surface orientations, namely, (100) and (111), were studied. sp3d5s* tight-binding model is used to calculate the band structures of GaSb MOSFET. Ballistic transport was studied using the semiclassical top-of-barrier model with applied self-consistent real-space potential across the body. First, we found that for (100) surface orientation, GaSb DG-UTB FET with body thickness of 24 ALs offered relatively larger ON-state current for various gate dielectric materials studied. However, for (111) surface orientation, 12 ALs GaSb DG-UTB FET showed the best performance due to its reasonably higher injection velocity and larger electron density. Furthermore, for the FET with a body thickness of 48 ALs and HfO2 dielectric, it was observed that the charge occupations shift toward the surface, unlike the cases of FETs with thinner body, leading to the formation of inversion charge on the surface. Finally, we compared the ON-state current of GaSb DG-UTB FET with different channel surface orientations and found that (100) surface generally outperforms (111) surface in terms of ON-state current. [ABSTRACT FROM AUTHOR]

We report the demonstration of a Ge0.95Sn0.05 on silicon (Ge0.95Sn0.05/Si) avalanche photodiode (APD) having a separate-absorption-charge-multiplication structure, wherein a Ge0.95Sn0.05 layer and a Si layer function as an absorption layer and a multiplication layer, respectively. Material characterization was performed by atomic force microscopy, X-ray diffraction, and transmission electron microscopy. The dark current Idark of the APD is dominated by the area-dependent bulk leakage rather than the surface leakage. The temperature dependence of breakdown voltage of the Ge0.95Sn0.05/Si APD was characterized and a thermal coefficient of 0.05% \mathrmK^\mathrm -1 was obtained, achieving a lower thermal sensitivity than the conventional III-V-based APDs. In the wavelength range of 1600–1630 nm, a responsivity of $\sim 1$ A/W (bias voltage {V}_{\rm bias} = -9.8 V) was achieved due to the internal avalanche gain. [ABSTRACT FROM PUBLISHER]