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In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

Vertical alignment liquid crystal (LC) cell driven by in-plane field with 3-D polymer network exhibited no pooling mura under an external mechanical pressure; however, the operating voltage of the device was increased, because the polymer network hinders field-induced reorientation of LC. In this paper, we adopted a modified cell structure in which a counter electrode on top substrate of the conventional mode is existed, to improve upon this drawback. The proposed device in which the polymer network is formed in bulk of vertically aligned LC layer shows a very fast response time of 2 ms (rise + decay), 57% reduction in operating voltage, and also keeps image quality although the cell is curved. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated. [ABSTRACT FROM PUBLISHER]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density. [ABSTRACT FROM AUTHOR]

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfOx/SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at 200~ ^\circ \text C > 4 \times 10^4 s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}} cycles) and ultralow switching current ( <0.1\mu \textA for RESET and <0.3\mu \textA for SET) are both demonstrated. The sub- \mu \textA switching current and self-selection nonlinear $I$ – V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( V_{O} ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation. [ABSTRACT FROM AUTHOR]

A statistical dependence of set voltage Vset on the preceding reset voltage $V_{{\rm {reset}}} is observed in resistive memory arrays and explained in terms of two interlocking mechanisms. This dependence can be replicated on a single device by intentionally varying the Vreset values by various linear voltage ramp rates. The latter mechanism is well modeled under the assumption that a critical heat deposited locally in the filament triggers the rupture of the filament. Mechanisms are proposed to explain the impact of different ramp rates of the reset operation on the ruptured gap in the filament that affect, in turn, the Vset value of the subsequent set operation. Based on these observations, a one-time tightening procedure is designed, leading to tightened Vset and V{\rm {reset}} distributions. [ABSTRACT FROM AUTHOR]

Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. Programming pulse voltage and width operating windows are identified for avoiding catastrophic pull-in. The simulation results indicate that sub-20-ns programming delay is possible with programming voltages compatible with standard input–output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is found to be effective for avoiding the issue of write disturbance. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) based on Cu or Ag filament is a promising selector device for high-density crosspoint arrays. These devices display high ON-OFF ratio, volatile switching, high switching speed, and long endurance, supporting the adoption in large memory arrays. However, the mechanism of volatile switching is not clear yet, which prevents the development of compact models for circuit design and simulation. Based on an extensive study of the switching mechanism, we report an analytical model that captures all electrical characteristics of the device, including switching, recovery, and their dependence on the applied voltage. We use the analytical model to simulate the circuit-level behavior of the device as long/short term memory synapse. [ABSTRACT FROM AUTHOR]

A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and electron hopping conduction transports are considered to model the conduction of RRAM. The model can reproduce both the typical I-V characteristics of RRAM in high-/low-resistance state (LRS) and the nonlinear characteristics in LRS. Moreover, to accurately model ac operation mode, the effects of parasitic capacitance and resistance are included in our model. The developed compact model is verified and calibrated by measured data in different HfOx-based RRAM devices under dc and ac operation modes. The excellent agreement between the model predictions and experimental results shows a promising prospect of the future implementation of this compact model in large-scale circuit simulation to optimize the design of RRAM. [ABSTRACT FROM PUBLISHER]

A polymer solid-electrolyte (PSE) switch has been embedded in a 90-nm-node CMOS featuring a forming-less programming and extremely high on/off ratio of \10^5. A fast programming of 10 ns is also demonstrated for 50-\nm\phi 1 k-b array by introducing the PSE switches integrated with a fully logic compatible process below 350 ^\circ\C. A high free volume in the PSE is supposed to result in the smooth formation of the Cu bridge without destroying the electrolyte, thereby also resulting in forming-less programming and high breakdown voltage. High disturbance reliability (T50; 50% fail) is extracted to be over 10 years at operation condition. The improved switching characteristics enable us to accurately program the crossbar circuit in a practical scale (32 \times 32) without cell transistors. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic. [ABSTRACT FROM AUTHOR]

Dual-layer resistive switching memory devices with WOx switching layer formed at the sidewall of the horizontal electrodes have been fabricated and characterized. The devices exhibit well-characterized analog switching characteristics and small mismatch in electrical characteristics for devices formed at the two layers. The 3-D vertical device structure allows higher storage density and larger connectivity for neuromorphic computing applications. We show that the vertical devices exhibit potentiation and depression characteristics similar to planar devices, and can be programmed independently with no crosstalk between the layers. [ABSTRACT FROM AUTHOR]