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This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

Enlargement of memory window through forming compliance current was demonstrated in Gd:SiO2 resistive random access memory (RRAM) with a gadolinium (Gd) electrode. Lower forming compliance current for Gd:SiO2 RRAM with a Gd electrode results in larger memory window as compared with the RRAM with a Pt electrode. Through analyses on the current conduction mechanism, we demonstrate that a lower forming compliance current leads to a thinner conductive filament forming and less oxygen ions penetrating into Gd electrode, which caused higher on current and lower off current. Furthermore, a possible resistive switching model was proposed to explain the effect of Gd electrode on RRAM device. [ABSTRACT FROM AUTHOR]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

Research on memory devices is a highly active field, and many new technologies are being constantly developed. However, characterizing them and understanding how to bias for optimal performance are becoming an increasingly tight bottleneck. Here, we propose a novel technique for extracting biasing parameters, conducive to desirable switching behavior in a highly automated manner, thereby shortening the process development cycles. The principle of operation is based on: 1) applying variable amplitude, pulse-mode stimulation on a test device in order to induce switching multiple times; 2) collecting the data on how pulsing parameters affect the device’s resistive state; and 3) choosing the most suitable biasing parameters for the application at hand. The utility of the proposed technique is validated on TiOx-based prototypes, where we demonstrate the successful extraction of biasing parameters that allow the operation of our devices both as multistate and binary resistive switches. [ABSTRACT FROM AUTHOR]

We report a 3-D-stackable 1S1R passive cross-point resistive random access memory (RRAM). The sneak (leakage) current challenge in the cross-point RRAM integration has been overcome utilizing a field-assisted superlinear threshold selector. The selector offers high selectivity of >10^7 , sharp switching slope of < 5 mV/decade, ability to tune the threshold voltage, stable operation at 125 °C, and endurance of >10^{11} . Furthermore, we demonstrate 1S1R integration in which the selector-subthreshold current is <10 pA while offering >10^2 memory ON/OFF ratio and >10^6 selectivity during cycling. Combined with self-current-controlled RRAM, the 1S1R enables high-density and high-performance memory applications. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

A bipolar, highly nonlinear n-p-n selector is coupled in series with resistive switching memory device to suppress the sneak path current. The memory characteristics are measured for the crossbar array fabricated on a flexible polyethylene terephthalate substrate. Dominant conduction mechanism is the Zener tunneling to obtain the high nonlinearity in the selector device. This phenomenon validates the ${I}$ – ${V}$ characteristics which are temperature dependent, which leads to decrease in the turn-on voltage of the device as the temperature increases. The proposed one bipolar selector-one resistor device demonstrates better memory characteristics with the high nonlinearity ($\sim 10^{\textsf {3}}$), observable memory window of about one order, excellent ac endurance ($10^{\textsf {7}}$) cycles, fast switching speed (60 ns), and stable retention ($10^{\textsf {4}}$ s) at 100 °C. The results show the substantial potential of the proposed one selector-one resistor structure in suppressing the leakage current, making it attractive for future high-density flexible crossbar memory array. [ABSTRACT FROM AUTHOR]

Physics-based compact models for redox-based resistive switching memory (ReRAM) devices are used to increase the physical understanding of the complex switching process as well as to allow for accurate circuit simulations. This includes that models have to cover devices showing bipolar switching (BS) and complementary switching (CS). In contrast to BS devices, which store the information in (at least) one high and one low resistance state, CS devices use (at least) two high resistance states. Applications of CS devices range from passive crossbar arrays to novel logic-in-memory concepts. The coexistence of CS and BS modes in one device has been shown experimentally. Here, a physics-based compact model describing BS and CS consistently is presented. Besides modeling CS devices, the model improves the description of BS as it allows to reproduce and explain anomalies in the BS RESET process. The model includes ion drift and diffusion along the filament. The influence of different parameters on the drift–diffusion balance is discussed. [ABSTRACT FROM AUTHOR]

Introducing a threshold switching selector in a resistive random access memory (RRAM) is essential for implementing a crossbar array that accurately accelerates neuromorphic computations. But, at an expense, a read voltage (${V}_{\text {read}}$) to be used for inference tasks is inevitably boosted. Therefore, this brief shows the effect of the enlarged ${V}_{\text {read}}$ on the stability of conductance states of the RRAM relevant to the inference robustness. The multiple conductance states of the analog RRAM achieved by a SPICE simulation are stable under consecutive 106 cycles of nominal ${V}_{\text {read}}$. However, each state of the one selector and one RRAM begins to be disturbed at ~104 cycles due to the boosted ${V}_{\text {read}}$. More importantly, when a certain state exceeds to the next state due to the accumulated ${V}_{\text {read}}$ stress, a classification accuracy of the neural network is significantly degraded. We, thus, introduce a two-step read scheme that separates the roles of turning on the selector and reading the states. As the selector is turned on rapidly with an additional large pulse, the following ${V}_{\text {read}}$ can be lowered. As a result, the read disturbance is minimized, and the optimized two-step pulse scheme allows 106 MNIST images to be recognized with >95% accuracy in the neural network. [ABSTRACT FROM AUTHOR]

The impact of the dielectric thickness, forming polarity, and current compliance on the self-rectifying current–voltage ( I – V ) characteristics of Ni/HfO2/n+-Si resistive random access memory (RRAM) devices was investigated. The obtained results indicate that these three aspects not only play a role in the postforming currents but also affect the switching properties of the devices. In the case of 5-nm-thick oxide devices, a self-rectifying ratio of about three orders or magnitude is observed after substrate injection forming (SIF) with current compliance below 500 $\mu$ A. However, similar devices subjected to gate injection forming (GIF) do not exhibit such rectifying feature. This distinctive behavior for SIF is ascribed to the formation of a Schottky-like contact in between the Ni-based conducting filament and the semiconductor electrode. For 20-nm-thick oxide devices, the forming voltage under GIF and the subsequent dielectric degradation are higher than for thinner oxide layers, resulting in a less resistive state, and a negligible role of the referred Schottky barrier. The effect of the temperature on the diffusion of the Ni ions that form the conducting path is also discussed. [ABSTRACT FROM PUBLISHER]

Filamentary conduction paths through insulating solid electrolytes is a widely accepted theory describing the conductionphenomenon in resistive random access memories (RRAMs). In this work, the relationship between filamentary conduction and multilevel resistive states obtained as a result of V\text {STOP} during the RESET process has been analyzed in detail to understand the underlying physics of resistive switching phenomenon. Subsequently, a multifilamentary conduction mechanism has been proposed and a “3-D multifilamentary rupturemodel” has been developed in a transition metal oxide-based RRAM. Four different resistance states have been achieved by using three conduction filaments and their subsequent rupture, thus realizing the multiple resistance levels. By varying V\text {STOP} , it has also been verified that the states thus obtained were because of the direct consequence of the conduction filaments. [ABSTRACT FROM PUBLISHER]

We propose a model describing the operations of hafnium oxide-based resistive random access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport are self-consistently described starting from the leakage current in pristine HfO2. Material structural modifications occurring during the RRAM operations, such as conductive filament (CF) creation and disruption, are accounted for. The model describes the complex processes leading to a formation of the CF and its dependence on both electrical conditions (e.g., current compliance, voltage stress, and temperature) and device characteristics (e.g., electrodes material and dielectric thickness). [ABSTRACT FROM AUTHOR]

Fully transparent and stable resistive switching characteristics in resistive random access memory (RRAM) device consisting of ITO/Ga doped ZnO (GZO)/ZnO/ITO architecture are proposed. The GZO nanorods with well aligned and extremely dense properties are considered as a thin film for RRAM device. The oxygen vacancies can be confined and migrate along grain boundaries in the GZO nanorod film. Therefore, the weakest point for formation and rupture of conductive filament can be limited at the interface between GZO nanorod film and ZnO seeding layer. Compared with ITO/ZnO/ITO device, a significant improvement in the distribution of high resistance state (HRS) and low resistance state (LRS) during resistance switching is demonstrated in the present device. In addition, a high endurance of more than 7000 cycles with the resistance ratios of HRS/LRS about 200 times is achieved in this device. The ITO/GZO/ZnO/ITO device is a good candidate for the transparent RRAM application. [ABSTRACT FROM PUBLISHER]

A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation. [ABSTRACT FROM AUTHOR]

Passive crossbar resistive random access memory (RRAM) arrays require select devices with nonlinear I-V characteristics to address the sneak-path problem. Here, we present a systematical analysis to evaluate the performance requirements of select devices during the read operation of RRAM arrays for the proposed one-selector-one-resistor (1S1R) configuration with serially connected selector/storage element. We found high selector current density is critical and the selector nonlinearity (ON/OFF) requirement can be relaxed at present. Different read schemes were analyzed to achieve high read margin and low power consumption. Design optimizations of the sense resistance and the storage elements are also discussed. [ABSTRACT FROM PUBLISHER]

A novel strategy based on defect engineering is proposed for high-performance multibit data storage in oxide-based resistive random access memory (RRAM). Key innovations are: 1) material-oriented cell engineering for desired modification of physical locations of generated oxygen vacancies in resistive switching layer; and 2) operation scheme to control the amount of oxygen vacancy generated in the conducting filament regions during switching. Proper doping approach is applied to suppress the formation of oxygen vacancy clusters due to the avalanching effect in the forming and set processes. Gradual resistive switching process is observed in the devices with proper doping at the proper switching operation modes. Multilevels of resistance states are measured by the optimized dc or ac switching mode. Excellent memory performance with four-level data storage (good resistance uniformity under pulse switching, retention > \10^4 s at 150 ^\circ \C, and endurance > \10^6 cycles) is successfully demonstrated in hafnium oxide-based RRAM devices, indicating the viability of the proposed engineering design strategy. The proposed methodology helps to understand the mechanism of multilevel switching and provides guidelines for the design of high-performance multibit resistive switching memory devices. [ABSTRACT FROM PUBLISHER]

The switching behaviors of the resistive switching device based on Ni-rich nickel oxide thin film during the set and reset processes in the pulse voltage experiment have been examined. In the switching from a high-resistance state (HRS) to a low-resistance state (LRS) during the set process, the formation of filament is the dominant process. The switching is easier to occur with a shorter off time between pulses, indicating that heat diffusion plays an important role. On the other hand, in the switching from the LRS to the HRS during the reset process, there is a competition between the formation and deformation of filament, which is much stronger than that in the set process. The heat diffusion during the off time between pulses affects both the formation and deformation of filaments. Thus, there is no definite relationship in statistics between the off time and the occurrence of the reset switching. [ABSTRACT FROM PUBLISHER]

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in neural networks. One of the key challenges for RRAM-based neural networks is to achieve bidirectional analog conductance modulation for online training. This article provides a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. We find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. We suggest that the filament morphology before SET may be the key to understanding this phenomenon; gradual SET is obtained when the filaments have a single-layer gap in the RESET state, and abrupt SET is obtained when the filaments have a multilayer gap in the RESET state. [ABSTRACT FROM AUTHOR]

The parallelism and analog computing features of neuromorphic systems bring great challenges in developing a compact model of analog resistive random access memory (RRAM). In this article, we develop a physics-based compact model for analog RRAM devices and crossbar array. Nonideal effects of analog RRAM device, such as variability, I – V nonlinearity, programming nonlinearity and asymmetry, and tuning voltage sensitivity, are modeled and verified with the statistical data measured from RRAM array. Modeling of parallel-vector-matrix-multiplication and weight update process on RRAM crossbars with interconnect resistance enables fast and accurate estimation of the training accuracy. Benchmarks of neural networks under different hardware conditions validate the functionality of the proposed model. This model can provide valuable design guidelines for a practical neuromorphic system with high performance and computing accuracy. [ABSTRACT FROM AUTHOR]

To understand the voltage–time dilemma in Pr0.7Ca0.3MnO3 (PCMO)-based resistive random access memory, we present switching transient currents for 10 ns–1 s for both SET and RESET. Three stages are observed during SET: 1) fast current (<100 ns) increase; 2) weak current increase; and 3) abrupt current increase to compliance. During RESET, four stages are observed: 1) fast increase in current; 2) fast reduction in the current; 3) current saturation; and 4) power law reduction of current with time. Such behavior is qualitatively independent of temperature. A qualitative mechanism is proposed. Furthermore, three implications on device performance are presented. First, the SET/RESET switching speed is limited by heating timescale to ~100 ns. Second, both SET and RESET read-disturb behaviors show exponential dependence on lower applied bias although RESET starts at lower bias in comparison to SET. This enables better immunity to read-disturb for high resistance state (HRS) on SET polarity. Third, SET transients are ambient temperature dependent, unlike RESET. This is consistent with the mechanism that during the SET process, the low current HRS does not produce a strong self-heating and, hence, depends upon ambient temperature. In comparison, during RESET process low-resistance state produces high current that enables intrinsic self-heating. Internally, generated high heat during RESET produces weak dependence on ambient temperature. [ABSTRACT FROM AUTHOR]

This brief investigated bipolar resistive switching (RS) characteristic of a top-electrode-free sol-gel SnOx resistive memory, which was fabricated at a low temperature of 120 °C. The RS characteristic was obtained by directly using a probe tip to make an electrical point contact with the SnOx surface. The SnOx memristor exhibited a remarkable memory window of 103 and it can operate over 500 dc cycles without noticeable degradation. Oxygen ion storage and release from a chemically active top-electrode, which were commonly used to explain RS, seem not applicable to this SnOx memristor. The SnOx film was characterized by X-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy, and ultraviolet-visible spectroscopy. The physical mechanisms of the conduction current and the RS behavior were also explored. [ABSTRACT FROM PUBLISHER]