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In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel–drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~106 even when the channel length is scaled to 7 nm. [ABSTRACT FROM PUBLISHER]

Ferroelectric (FE) hafnium oxide is a promising candidate for memory applications. In this paper, endurance, imprint, and retention tests are carried out on FE aluminum-doped hafnium oxide thin films with different electrodes: 1) metal–insulator–metal (MIM) and 2) silicon–insulator–silicon(SIS). MIM devices exhibit higher endurance than SIS devices. However, SIS devices show superior imprint and retention, with an extrapolated retention time-to-failure larger than 10 years at 85 °C. These results are very promising to integrate FE-HfO2 in 3-D structures, either for dynamic random access memory or for NAND applications. [ABSTRACT FROM PUBLISHER]

In this paper, we reported a ferroelectric HfAlOx negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlOx transistor with GS engineering percentage of $\text{I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement and 27% $\text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. [ABSTRACT FROM AUTHOR]

We study in detail the impact of alloying HfO2 with Al (Hf1–xAl2xO2+x) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed comprehensive diffusion barrier calculations in HfO2, Hf1–xAl2xO2+x, and Hf1–xTixO2 relative to the oxygen vacancy ( Vo ) movement involved in low-resistance state ( R\mathrm{\scriptscriptstyle ON} ) thermal stability. Calculations are performed at the best level using ab initio techniques. This paper provides an insight on the improved R\mathrm{\scriptscriptstyle ON} stability of our Hf1–xAl2xO2+x-based RRAM devices and predicts the degraded retention of Hf1–xTixO2-based RRAM measured in the literature. Our theoretical calculations link the origin of R\mathrm{\scriptscriptstyle ON} retention failure to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in HfO2-based RRAM. [ABSTRACT FROM PUBLISHER]

This paper discusses in detail the effects of device dimensions and layout/design rules on the analog performance of gate-first high- $K$ gate dielectrics and metal gate (HKMG) nMOS transistors. It is observed through detailed measurements that the transconductance of HKMG nMOS transistors increases with the reduction in the channel width. The 80-nm wide HKMG nMOS transistors show $1.3\times $ improvement in the intrinsic gain and $\sim 27$ % improvement in the transconductance generation efficiency compared with a 1000-nm wide transistor. The similar behavior is observed for all gate lengths. The physical mechanisms responsible for this behavior are identified and explained. It is finally shown that the analog performance of the HKMG nMOS transistors could be further improved by dividing a single active finger into multiple active fingers, by increasing active-to-active spacing, by increasing the gate pitch, and by eliminating the active dummies. [ABSTRACT FROM AUTHOR]

In this paper, the first demonstration of a bow-tie antenna integrated with a metal–insulator–metal (MIM) diode for electromagnetic energy harvesting in the ${V}$ -band (i.e., 40–75 GHz) is presented. We have designed, simulated, fabricated, and fully characterized a 60-GHz rectifying antenna (rectenna) based on a vertical Au-HfO2-Pt MIM diode with reduced differential resistance. The dielectric used for the MIM structure is a 6-nm-thick amorphous HfO2 grown by atomic layer deposition. For the fabricated MIM device, we report here a current density of ${3} \times {10}^{ {4}}$ A/cm2 that exceeds the previous values presented in the literature. The vertical MIM-based rectenna is able to efficiently harvest up to $250~\mu \text{V}$ from an impinging modulated millimeter-wave signal with −20 dBm of available power, thus offering a voltage responsivity of over 5 V/W. The reported results indicate that the proposed approach is well suited for future low-power solutions much sought after for the energetically autonomous 5G terminal equipment. [ABSTRACT FROM AUTHOR]

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125°C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the link between various resistive memory (RRAM) electrical characteristics: endurance, window margin (WM), and retention. For this purpose, several RRAMs are characterized using various resistive layers and bottom electrodes. By focusing on one technology and optimizing programming conditions (current, voltage, and time), we establish a tradeoff between endurance and WM. Then, by changing memory stack, we demonstrate the correlation between endurance plus window marging improvement and retention degradation. Studying this last feature from a material point of view, we analyze different oxides by density functional theory. We realize a systematic review for possible exchanges of species between resistive layer and Cu-based top electrode and study their diffusion. This provides insights on conductive filament composition in different stacks. Combining previous experiments and simulations, we propose a link between memory characteristics and material microscopic parameters, through the ion energy migration barrier. Finally, we extract how endurance, WM, and retention are correlated to material properties and electrical parameters in order to choose the suitable material for a defined application using the RRAM technology. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

This paper analyzes and models the narrow width effect (NWE) observed in nMOS transistors fabricated using a 28-nm gate-first CMOS process. It is shown that the threshold voltage of nMOS transistors increases with decrease in channel width and this effect is enhanced at shorter gate lengths, thicker hafnium oxide (HfO2), and thicker lanthanum (La) capping layer. It is also observed that this increase in threshold voltage for narrow width transistors is influenced by the device layout. The physical mechanisms responsible for the observed anomalous behavior are identified through measurements on different test structures. An empirical model is proposed to understand and model this behavior. The accuracy of the model is verified by comparing it with the experimental data. It is finally proposed that the observed NWE could be minimized by optimizing the thickness of HfO2, La capping layer, and SiO2 interfacial layer and by using different device layouts. [ABSTRACT FROM PUBLISHER]

In this paper, we propose for the first time an attractive Si3N4/laminated Al2O3–HfO2 (LAHO) stack metal–insulator–metal (MIM) capacitor with a low-leakage characteristic, good voltage linearity, high capacitance density, and excellent time-dependent dielectric breakdown (TDDB) reliability. The capacitor demonstrates a capacitance density of 4.2 fF/ \(\mu \) m \(^{\mathrm {\mathbf {2}}}\) , quadratic voltage coefficients ( \(\alpha \) ) of 106 ppm/V \(^{\mathrm {\mathbf {2}}}\) , and 18.92-year TDDB lifetime under a stressing voltage of 6.6 V. For the extended performance, it is projected that such a capacitor can possess a maximum capacitance density of 4.13 fF/ \(\mu \) m \(^{\mathrm {\mathbf {2}}}\) with \(\alpha \le 100\) ppm/V \(^{\mathrm {\mathbf {2}}}\) and TDDB lifetime of 10 years under an analog operation of 7 V. Furthermore, this paper shows that \(\alpha \) and TDDB lifetime of the new capacitor are very sensitive to the thickness of the Si3N4 film. Comparison of the new MIM capacitors with the SiO2/HfO2 stack MIM capacitors shows that the SiO2/HfO2 capacitor is more suitable for low-voltage applications, whereas the new Si3N4/LAHO capacitor is superior for operations requiring a higher biasing condition. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

Low-frequency noise analysis is being used as a method to understand the nature of carrier transport in new material-based devices and to improve the sensitivity of sensors operating in the subthreshold regime. In this paper, we show that the (\rmgm/\rmId)^2 method used in carrier number fluctuation based noise formulation needs modification in the subthreshold regime. Based on the new formulation, many published results may require reinterpretation. The new formulation is validated with data extracted from the literature for III–V, nanowire, and high-K gate-stack-based devices. [ABSTRACT FROM PUBLISHER]

To achieve low power consumption for CMOS devices, the gate metals must have effective work function (EWF) aligned with the band edges of the channel material and have a small WF variation (WFV). The multilayer TiNi alloys have been successfully applied as the gate metals for HfO2/In0.53Ga0.47As MOS devices in this paper. The EWF of TiNi alloys was found to increase from 4.41 eV for as-deposited sample to 4.62 eV after the alloy was annealed due to the diffusion of Ni atoms into Ti layer. The multilayer TiNi alloy remained amorphous phase with small WFV until annealed at 600 °C. The TiNi alloy is thermally more stable as compared with either Ti or Ni metal, because the TiOxNi interfacial layer prevents the diffusion of Ni atoms into HfO2 film and the further reaction of Ti with HfO2. The results can be applied for InGaAs nMOS fabrication. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

In this paper, the presence of filamentary current instabilities in the high resistance state of Ni/HfO2-based RRAM devices and their associated current fluctuations mechanisms are explored. After systematic measurements, the advanced weighted time-lag plot method is employed to accurately identify the contribution of multiple electrically active defects and to minimize the negative effect of the background noise. Special attention is given to the physical analysis of multilevel random telegraph noise (RTN) signals caused by both independent and interactive defects located in the vicinity of the conductive filament (CF), which may alter the tunneling path and induce large stochastic current fluctuations. In addition, irreversible current changes, owing to trap density variations inside or near the CF, are also identified. Finally, the voltage dependence of the RTN phenomena and the occurrence of stress-induced complex fluctuations is evaluated. [ABSTRACT FROM PUBLISHER]

In this paper, we investigated the electrical properties of a metal-induced laterally crystallized (MILC) p-type low-temperature polycrystalline-silicon thin-film transistor (LTPS-TFT) using high- \kappa ZrTiO4 (ZTO) gate dielectric. With the orthorhombic-ZTO (111) preferred crystal system, the gate-stack with a low equivalent-oxide-thickness (EOT) of 4.1 nm and high permittivity of 50 achieve high dielectric quality by showing a low interfacial trap density ( N_{\mathrm{ it}}) of 3.5\times 10^{11} cm ^-2 eV ^-1 near the mid-gap traps. From these results, the MILC p-type LTPS-TFT exhibits a record subthreshold slope of 80 mV/decade, which is attributed to the low N\mathrm{ it} and EOT. In addition, the high-hole field-effect mobility of 250 cm2/Vsec at 1 MV/cm and high I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} ratio of 1.5\times 10^8 were observed. From the reliability evaluation, the degradation in the positive-bias stress, hot-carrier stress, and self-heating stress was dramatically superior to the conventional LTPS-TFT with SiO2 gate dielectric. These results confirm that the ZTO dielectric holds a great potential for the next-generation LTPS-TFTs. [ABSTRACT FROM AUTHOR]

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( L\mathrm{eff} ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

Hf0.5Zr0.5O2 (HfZrO) thin-film ferroelectric materials have recently drawn considerable attention due to their attractive properties such as large bandgap (>5 eV), extreme thin thickness ( ${\le} 10$ nm), and good Si-compatibility. However, high crystallization temperature (600 °C–1000 °C) and relatively low remanent polarization ( ${P}_{r}$ ) compared to conventional perovskite ferroelectric materials are not suitable for flexible energy related devices, and are insufficient to overcome the barriers of conventional ferroelectric memory. In this paper, we investigated the effect of high-pressure postmetallization annealing (HPPMA) on the ferroelectric properties of the HfZrO metal–ferroelectric–metal (MFM) devices. HfZrO MFM capacitors annealed at 450 °C/50 bar shows a ${P}_{r}$ value of over 20 $\mu \text{C}$ /cm2 which is very advanced ${P}_{r}$ value. Based on the short-pulse switching technique, we quantitatively and systematically examined the improved characteristics of HfZrO prepared by HPPMA in terms of coercive field ( ${E}_{c}$ ) and possibly involved interfacial capacitance ( ${C}_{i}$ ). [ABSTRACT FROM AUTHOR]

This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS transistors fabricated using 28-nm gate-first High- K metal gate CMOS technology. It is shown that the PBTI reduces with decrease in width ( W ), increase in capping layer thickness and decrease in high- K dielectric thickness. The physical mechanisms responsible for these dependencies are investigated and attributed to the modulation of preexisting traps in the high- K dielectric and the modulation of electron injection into these traps. It is also shown that the PBTI of the devices could be improved by dividing a single active into multiple actives, by increasing active-to-active spacing and gate pitch. [ABSTRACT FROM PUBLISHER]

A Ge MOS device with an ultralow equivalent oxide thickness of \(\sim 0.5\) nm and acceptable leakage current of 0.5 A/cm \(^{{2}}\) is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher \(k\) value ( \(k\sim 31\) ) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 ( \(t\) -HfO2) also shows a lower leakage current and better thermal stability. The mechanisms for \(t\) -HfO2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by \({\boldsymbol { {in~situ}}}\) interfacial layer (IL) formation and high- \(k\) processes. The IL with \(k\sim 13\) can be formed by in situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge \(^{{+4}}\) . [ABSTRACT FROM AUTHOR]

Positive bias temperature instability (PBTI) has become one of the major reliability concerns in the present day CMOS technology. The PBTI mostly degrades the performance of high- \(\kappa \) /metal gate (HK/MG) nMOSFETs and is dominated by time dependent stress induced trap generation. The PBTI models proposed so far in different literature are deterministic in nature and overlook the randomness of the temporal degradation of transistor threshold voltage, \(V_{\rm th}\) . In this paper, we present a stochastic model for PBTI to predict the behavior of HK/MG nMOSFETs under inversion mode stress. The model is scalable and is verified against experimental data from two different groups. Our model separately considers each trap to predict their impact on device performance. The simulations are carried out at accelerated voltage and temperature conditions and we noted the variations in \(V_{\rm th}\) . In addition, we have analyzed the impact of PBTI on the performance of a ring oscillator and concluded that the circuit speed suffers significant degradation due to this effect. We have also observed that the adverse effect of PBTI becomes more severe as we go deeper into the nanometer technology. [ABSTRACT FROM AUTHOR]

In this paper, the trapping properties of HfO2 -based charge-trap cells have been extensively studied by means of a synergic use of material analysis, electrical characterization, and electrical and atomistic modeling. We assessed the impact of process conditions [i.e., postdeposition annealing (PDA)] on the material structure and the trapping behavior of the fabricated gate-stacks. Furthermore, we present reliable models for the HfO2 structure and for the defects responsible for the electron trapping. We found that HfO2 has a trap density comparable with that of SiN that depends on the PDA temperature. The HfO2 traps are shallower in energy than SiN traps, but retention of memory cells is still sufficient, also because of a slightly larger electron affinity and a larger permittivity than SiN that allows thicker layers while preserving the equivalent oxide thickness of the gate-stack. [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of an atomic layer-deposited Y2O3 dielectric on the passivation of a GeO2 layer in GeO2-based Ge gate stacks. The equivalent oxide thickness scalability and thermal stability of the ultrathin Y2O3 layer are evaluated at different Y2O3 thicknesses and annealing conditions in detail. Experimental results show that a Y2O3 layer thickness of 1.0 nm is required to serve as a GeO2 passivation layer while retaining gate-stack performance at 400 °C postdeposition annealing. However, at a higher annealing temperature of 500 °C, the barrier property deteriorates and allows GeO desorption. The proposed gate-stack implies the applicability of a Y2O3 passivation method for further scaled GeO2-based Ge gate stacks. [ABSTRACT FROM PUBLISHER]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

We investigate p-type GaSb MOS capacitors with various HfO2 thicknesses grown using an atomic layer deposition. GaSb surfaces treated with ex-situ chemical solution and in situ remote hydrogen plasma are inspected. After a series of etching steps, the GaSb surfaces exhibit smooth topography, indicating that this combination of treatments is capable of realizing ultrathin dielectric deposition. After etching processes, the ultrathin (approximately 3 nm) HfO2 layer deposited successfully on GaSb exhibit high-permittivity (approximately 21) properties as well as equivalent oxide thickness (EOT) of 0.75 nm, which can be attributed to the flat surface. To the best of our knowledge, the EOT of GaSb capacitor prepared using the exploited approach is record low. Furthermore, we find that the interlayer present after hydrogen plasma treatment and forming gas annealing could efficiently passivate interface state density and achieve high $C$ – $V$ modulation. Compared with the benchmark of gate leakage current versus EOT, the electrical performance with low gate leakage current of the GaSb MOS capacitors demonstrates the high feasibility of the proposed treatments. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

Limited endurance of resistive RAM (RRAM) is a major challenge for future computing systems. Using thorough endurance tests that incorporate fine-grained read operations at the array level, we quantify for the first time temporary write failures (TWFs) caused by intrinsic RRAM cycle-to-cycle and cell-to-cell variations. We also quantify permanent write failures (PWFs) caused by irreversible breakdown/dissolution of the conductive filament. We show how technology-, RRAM programing-, and system resilience-level solutions can be effectively combined to design new generations of energy-efficient computing systems that can successfully run deep learning (and other machine learning) applications despite TWFs and PWFs. We analyze corresponding system lifetimes and TWF bit error ratio. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

This paper reports on results of modeling of current-voltage characteristics of the Ag/ZnO/TiAu planar Schottky diodes containing interfacial layer of hafnium dioxide (HfO2) with thickness ranging from 1.25 to 7.5 nm. It was found that forward characteristics can be described with thermionic emission theory. In this way, values of some relevant diodes’ parameters were determined, including the ideality factor and the effective Schottky barrier height. We found a satisfactory agreement of experimental and theoretical results for most diodes, with exception of the one with a 7.5-nm thick layer. It was found that a 2.5-nm thick HfO2 spacer between ZnO and silver contact yields the highest effective Schottky barrier height ( $\sim 0.7$ eV) accompanied by a pronounced rectification ratio (reaching 7 \times 10^{2} at ±2.5 V) of the examined planar structure. [ABSTRACT FROM AUTHOR]

A scalable process that can yield low-resistance contacts to transition metal dichalcogenides is crucial for realizing a viable device technology from these materials. Here, we systematically examine the effect of high-k dielectric-mediated doping on key device metrics including contact resistance and carrier mobility. Specifically, we use top-gated transistors from monolayer MoS2 as a test vehicle and vary the MoS2 doping level by adjusting the amount of oxygen vacancies in the HfOx gate dielectric. To understand the effect of doping on the contact resistance, from a fundamental standpoint, we first estimate the doping level in monolayer MoS2. The results of our device studies quantitatively show that the reduction in contact resistance with an increase in doping is due to the doping-induced lowering of the Schottky barrier height (SBH) at the metal–semiconductor interface. Furthermore, our temperature-dependent measurements reveal that a mixture of thermionic and field emissions, even at high carrier densities, dominates carrier conduction at the contact. While our study reveals the effectiveness of dielectric-induced doping in lowering SBH, it suggests that a further reduction of SBH using alternative methods is necessary for achieving an ohmic-like contact to monolayer MoS2. [ABSTRACT FROM AUTHOR]

The recently discovered ferroelectric behavior of HfO2-based dielectrics yields the potential to overcome the main challenges of the ferroelectric field-effect transistors (FeFETs)—CMOS compatibility as well as scalability to the state-of-the-art technology nodes of logic transistors. In this paper, we study the impact of scaling on the memory performance of FeFET devices employing Si:HfO2 ferroelectric films. The operation capability was proven down to a gate length of 28 nm. Program/erase characteristics, endurance behavior, and retention properties were analyzed for FeFETs with gate lengths scaled down to 32 nm. The detected difference in the performance between the long and short channel devices could be for the most part attributed to transistor short channel effects. In addition, the effect of temperature on the device properties of Si:HfO2-based FeFETs was investigated in detail. The program/erase speed was ascertained to be independent of temperature. On the other hand, increase in temperature resulted in reduced initial memory window accompanied by its slightly accelerated decay with time. [ABSTRACT FROM AUTHOR]

We propose a physical model for the fast component ( \(<1\) s) of the positive bias temperature instability (PBTI) process in SiOx/HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the \(V_{\mathrm {{TH}}}\) shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies). [ABSTRACT FROM AUTHOR]

Aluminum doped HfO2 (HfAlO) prepared by atomic layer deposition is investigated as gate dielectric for low-voltage organic thin-film transistors (OTFTs). The HfAlO film exhibits a low leakage current density of \(4.92 \times 10^{-8}\) A/cm \(^{2}\) at −3 MV/cm, which is \(\sim 70\) % smaller than its HfO2 counterpart. In addition, copper phthalocyanine (CuPc) OTFT with HfAlO dielectric has an average mobility \(\mu ~(2.58\pm 0.32\times 10^{-3}\) cm \(^{2}\) /Vs) increased by 58%, sub-threshold slope SS (0.9 ± 0.11 V/decade) decreased by 11%, and ON/OFF ratio \(I_{\mathrm{{\scriptstyle ON}}}/I_{\mathrm{{\scriptstyle OFF}}}\) (3.1 ± 1.3 \(\times \) \( 10^{3}\) ) increased by 86% as compared with those with HfO2 as gate dielectric ( \(\mu =1.63\pm 0.27\times 10^{-3}\) cm \(^{2}\) /Vs; \({\rm SS}=1.01\) ±0.1 V/decade; \(I_{\mathrm{{\scriptstyle ON}}}/I_{\mathrm{{\scriptstyle OFF}}}=1.7\pm 0.77\times 10^{3}\) ). All these could be ascribed to the inclusion of Al in the HfO2 film, which increases the conduction band offset and the bandgap and improves the dielectric and interface quality. The temperature effect on the performance of OTFTs is also investigated. [ABSTRACT FROM AUTHOR]

The high performance Ge pMOSFETs have been realized with ultrathin HfO2/AlOx/GeOx/Ge gate-stacks fabricated by ozone postoxidation (OPO) and NiGe metal source/drain (S/D). It is found that OPO yields a reduction of interface traps and an improvement of dielectric strength for the HfO2/AlOx/GeOx/Ge gate-stacks. On the other hand, it is also confirmed that the NiGe metal S/D structure decreases the S/D parasitic resistance severely. As a result, the record high drive current has been realized under a comparable gate length for present Ge pMOSFET structure with the ultrathin equivalent oxide thickness HfO2/AlOx/GeOx/Ge gate-stack and the low parasitic resistance NiGe S/D. [ABSTRACT FROM AUTHOR]

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) is widely considered as a disruptive technology. Despite tremendous efforts in theoretical modeling and physical analysis, details of how the conductive filament (CF) in metal-oxide-based filamentary RRAM devices is modified during normal device operations remain speculative, because direct experimental evidence at defect level has been missing. In this paper, a random-telegraph-signal-based defect-tracking technique (RDT) is developed for probing the location and movements of individual defects and their statistical spatial and energy characteristics in the CF of state-of-the-art hafnium-oxide RRAM devices. For the first time, the critical filament region of the CF is experimentally identified, which is located near, but not at, the bottom electrode with a length of nanometer scale. We demonstrate with the RDT technique that the modification of this key constriction region by defect movements can be observed and correlated with switching operation conditions, providing insight into the resistive switching mechanism. [ABSTRACT FROM PUBLISHER]

The basic analog parameters of three splits of InxGa1–xAs nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO2/1-nm Al2O3 gate. The low equivalent oxide thickness improves the electrostatic coupling, enhancing I{\text {DS}} , and, consequently, also gm and AV , especially for higher \text V{\text {GS}} . The InGaAs tunnel field-effect transistors (TFETs) show compatible performance with Si TFETs, and have better performance than Si MOSFETs, making them useful for low-power and low-voltage analog applications. The highest efficiency is found using the combination of a 2-nm HfO2 with In0.53Ga0.47As, due to the 56-mV/dec subthreshold swing obtained. For all splits, the AV peak can be related to the V{\text {GS}} necessary for band-to-band tunneling to become the dominant transport mechanism. [ABSTRACT FROM PUBLISHER]

Controlling threshold voltage variation during fabrication is essential, and one source for the variation is the thermal instability of valence band offset (VBO) for HfO2 deposited on Si. It has been reported that VBO can be changed as much as 0.33-0.60 eV after annealing. This paper proposes a hybrid process with both H2O and ozone as oxygen source during the deposition of HfO2 film. X-ray photoelectron spectroscopy shows that the VBO of this hybrid-fabricated film changes as little as 0.02 eV after a 600 °C anneal, which is compatible with the gate-last process. The improved stability is further confirmed by the VFB extracted from the C-V measurement. The physical processes that may be responsible for this improvement are discussed. [ABSTRACT FROM AUTHOR]

This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the NMOS transistors increase with the decrease in the channel width, and this effect is enhanced at shorter gate lengths. PMOS transistors show conventional width dependence. The possible physical mechanisms responsible for this anomalous behavior are identified and explained through detailed measurements. A 2-D charge-distribution-based model is proposed to model this anomalous effect. The accuracy of the proposed model is verified by comparing it with the experimental and simulated data. [ABSTRACT FROM PUBLISHER]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

Effects of a TiN gate electrode on interface trap density, bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB) in HfSiON metal–oxide–semiconductor field-effect transistors are investigated in this paper. Based on experimental data, we found that the TiN metal gate electrode thickness plays an important role in determining the final dielectric stability and the interface quality. Samples with thicker TiN gate electrode, which prevent oxygen diffusion from the high-\kappa layers toward the \alpha-Si electrode, exhibit a lower Dit level. In addition, the levels of oxygen vacancies are expected to be suppressed by thicker TiN gate electrode, which subsequently alleviates damage at the \Si/SiO2 interface and improves both the BTI and TDDB performances. [ABSTRACT FROM PUBLISHER]

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO{2} gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO{2}/poly-Si interface. P-channel LTPS-TFT has much higher Idrv\sim 0.789~mA than the n-channel LTPS-TFT \sim0.274~mA under the same overdrive gate voltage. This asymmetric Idrv is due to the characteristics of field effect mobility \muFE that p-channel LTPS-TFT has much higher hole \muFE\sim 80.16~cm^{{2}}/Vs than the electron \muFE\sim 38.26~cm^{{2}}/V~s of n-channel LTPS-TFT. The modification of HfO{2}/poly-Si interface by O{2} plasma can enhance the electron \muFE\sim {34\%} and reduce the hole \muFE\sim{22.4\%}, resulting in balanced Idrv of CMOS LTPS-TFTs that n-channel device shows Idrv\sim 0.553~mA and p-channel device shows Idrv\sim 0.590~mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO{2} gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

We investigate in detail the effects of metal electrodes on the switching performance and conductive filament (CF) stability of HfO2-based RRAM. The current–voltage characteristics of the devices exhibit different electrode-dependent RESET profiles which we attempt to clarify. With the insight from the experimental data, we employ first-principles calculations to have a better microscopic understanding of the devices. We study the charge injection, formation of Frenkel pairs, and diffusion of oxygen defects (oxygen vacancies Vo and oxygen interstitials Oi) that are important in the CF creation and stability during the device operation. Since the presence of Ti in RRAM has been associated with the creation of substoichiometric TiOy region at the Ti/HfO2 interface, we also explore different Ti and Hf suboxides to understand the possible composition of that interface. Our calculations suggest that the composition of the interface would be Ti2O/Hf2O3 from thermodynamic perspective. By combining the experimental and calculations results, we show that the concentration of oxygen interstitial (Oi) ions in the oxide after CF formation is larger for RRAM devices with inert electrodes (like Pt) compared with O reactive electrodes (like Ti) which results in degraded device performance. The lower Oi concentration in HfO2 layer with Ti electrodes results in improved CF thermal stability and device variability. [ABSTRACT FROM AUTHOR]

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high- $k$ (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm. [ABSTRACT FROM PUBLISHER]