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This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

A comprehensive study of dielectric modulated (DM) drift regions for power devices is presented in this paper. The performance of this structure is theoretically analyzed and compared with both conventional and superjunction (SJ) structures. In this paper, an analytical model for DM drift regions with cylindrical cells is proposed and compared with linear cells. An optimal tradeoff between breakdown voltage (BV) and specific ON-resistance ( R\scriptscriptstyle ON,sp) is obtained by a methodology developed in this paper. 3-D simulations of DM structures with hexagonal cells approximated by cylindrical cells are conducted to verify the analytical model. Optimal BV– R\scriptscriptstyle ON,sp tradeoffs for devices with conventional and SJ drift regions are also obtained through the same methodology and verified by 3-D simulations. Static characteristics of these three different drift region structures in both Si and SiC power devices are compared. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs). [ABSTRACT FROM AUTHOR]

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with I\mathrm{\scriptscriptstyle ON} of a few \mu \textA / \mu \textm for |V\mathrm {\mathbf {DS}}| = |V\mathrm {\mathbf {GS}}| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS. [ABSTRACT FROM AUTHOR]

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures. [ABSTRACT FROM AUTHOR]

In this paper, we study the switching behavior of silicon-on-insulator light-emitting diodes (LEDs). Through the comparison of various device geometries, we establish the dimensional dependence of the switching speed of the LED. TCAD simulations are in line with the experimental results. Our findings indicate that ON–OFF keying up to GHz frequencies should be feasible with such diodes, although a design optimized for higher frequency operation will exhibit a reduced light emission efficiency. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

Recently demonstrated CMOS circuits based on Ge nanowires (Ge-FET) promise sustained technology scaling because higher mobility Ge guarantees target ${I}_{\text {ON}}$ at a lower ${V}_{{\textit {DD}}}$. Unfortunately, this promise is counterbalanced by the fact that Ge is a poor thermal conductor, thus, the thermal confinement of the surround-gate topology may exacerbate self-heating (SHE) and erode the intrinsic performance gain associated with the high channel mobility. In this paper, we use: 1) electrical and optical methods to, respectively, characterize channel and surface SHE of Ge-FET with various channel lengths ( ${L}_{\text {ch}}$ ), widths ( ${W}_{\text {ch}}$ ), and the number of the nanowires (NWs) (#NW); 2) interpret the results obtained by the 3-D thermal modeling, and compare theoretically the SHE in Ge-FET configured in various topologies, such as bulk FinFET, silicon-on-insulator FinFET, and gate-all-around NW-FET; and 3) embed the results in an electrothermal SPICE simulator to compare the performance of ring oscillators based on Ge-FET and Si-FET. Our results show that the existing Ge-FET (with an airgap) is thermally suboptimal, but once optimized, SHE in Ge-FET would be comparable to that of Si-FET. The results encourage sustained development of Ge-FETs. [ABSTRACT FROM AUTHOR]

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique to overcome the conductance limitation in metal contacted single-walled carbon nanotubes (SWNTs)-based devices using metal nanoparticles (MNPs). Schottky barrier (SB) height at metal-SWNTs contact is believed to be the major contributor for this conductance limitation. Metal contacts with SWNTs are fabricated on a thermally grown SiO2/Si substrate using a conventional lithography process. The SWNTs are aligned between the metal electrodes using dielectrophoresis method. MNPs are introduced in the device using a small drop of MNP suspension to decorate the SWNTs. It is observed that the introduction of MNPs in the device reduces the SB height significantly. We found 0.34 eV reduction in SB height with silver (Ag) nanoparticles (NPs) and 0.15 eV with gold (Au) NPs. The proposed technique has improved the conductance in decorated SWNTs four times for Ag and Au NPs as compared to the bare SWNTs. Improvement in the conductance behavior of the SWNTs using MNPs enhances the sensitivity and switching speed of the devices, therefore, make it a promising alternative to silicon-based devices. [ABSTRACT FROM AUTHOR]

This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications. [ABSTRACT FROM AUTHOR]

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of $10~\mu \text{s}$ or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in “pseudo” charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length ($\lambda $) by varying the silicon film (${t}_{\textsf {Si},\textsf {v}}$) and the oxide (${t}_{\textsf {Si},\textsf {v}}$) thicknesses at the channel–drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) and significantly suppressed ambipolar leakage (${I}_{\textsf {AMB}}$) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , 73% increase in transconductance (${g}_{\textsf {m}}$), 62% increase in cutoff frequency (${f}_{\textsf {T}}$), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay (${t}_{\textsf {pHL}}$) are achieved in the proposed device. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances. [ABSTRACT FROM AUTHOR]

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB. [ABSTRACT FROM AUTHOR]

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer. [ABSTRACT FROM AUTHOR]

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by ${P}_{\text {max}}/A$ , which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. ${P}_{\text {max}}$ is dependent on the snapback voltage (${V}_{\text {sb,QS}}$), OFF-state breakdown voltage (${V}_{\text {bd}, \mathrm{\scriptscriptstyle OFF}}$), and maximum current (${I}_{\text {max}}$) in the quasi-saturation regime of an LDMOS transistor. Increase of ${P}_{\text {max}}/A$ by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on ${V}_{\text {sb,QS}}$ and ${P}_{\text {max}}/A$ are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process. [ABSTRACT FROM PUBLISHER]

A new concept of vertical gallium nitride (GaN) Schottky barrier diode based on nanowire (NW) structures and the principle of dielectric REduced SURface Field (RESURF) is proposed in this paper. High-threading dislocation density in GaN epitaxy grown on foreign substrates has hindered the development and commercialization of vertical GaN power devices. The proposed NW structure, previously explored for LEDs offers an opportunity to reduce defect density and fabricate low cost vertical GaN power devices on silicon (Si) substrates. In this paper, we investigate the static characteristics of high-voltage GaN NW Schottky diodes using 3-D TCAD device simulation. The NW architecture theoretically achieves blocking voltages upward of 700 V with very low specific on-resistance. Two different methods of device fabrication are discussed. Preliminary experimental results are reported on device samples fabricated using one of the proposed methods. The fabricated Schottky diodes exhibit a breakdown voltage of around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, the preliminary results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture and a foreign substrate. The proposed NW approach has the potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s high electron mobility transistors (HEMTs) technology and vertical GaN on GaN devices. [ABSTRACT FROM PUBLISHER]

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications. [ABSTRACT FROM PUBLISHER]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

Silicon heterojunction solar cells having semiconducting oxide-selective contacts can revolutionize the photovoltaic industry with the promise of low cost and high efficiency. In this paper, we have identified the potential design issues of silicon heterojunction cell using simulation. This paper compares two possible electron-selective oxides (TiO2 and ZnO) and two possible hole-selective oxides (CuAlO2 and NiO). The Fermi level in the oxide at the oxide/metal interface is pinned by the metal (its workfunction and eventual interface dipoles). We considered this effect, which determines the effective workfunction of the metal contact as opposed to the actual metal workfunction. Our simulation suggests that Fermi level pinning has significant impact on the device performance. We also considered different interface passivation effects and oxide dopings in our simulation. The simulation suggests that high doping in oxides is beneficial to counter balance the effect of poor surface passivation. This paper provides an extensive understanding of the design of Si heterojunction solar cell using band-engineered semiconducting oxide as the selective contact replacing highly doped emitter and back surface field. [ABSTRACT FROM PUBLISHER]

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more. [ABSTRACT FROM AUTHOR]

Thanks to the high electron velocities, III–V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As , and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III–V and Si nanoscale MOSFETs with a given gate length (L{G}) may have a quite different effective channel length (Leff) ; 2) the difference in Leff provides a useful insight to interpret the performance comparison of III–V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III–V MOSFETs. [ABSTRACT FROM AUTHOR]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance. [ABSTRACT FROM PUBLISHER]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( V^0 ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS. [ABSTRACT FROM AUTHOR]

This paper presents the wideband modeling and analysis of differential through-silicon vias (D-TSVs) in 3-D ICs. An equivalent-circuit model of the ground–signal–signal–ground-type D-TSVs is given and validated against a commercial full-wave electromagnetic simulation tool. The common- and differential-mode impedances are extracted using the partial-element equivalent-circuit method, while the admittances are calculated analytically, with the MOS effects considered and treated appropriately. The circuit model can also be used for studying the differential annular TSVs (ATSVs). It is shown that the ATSVs are more suitable for transmitting differential signals in comparison with the cylindrical TSVs. Based on the equivalent-circuit model, the characteristic impedances and the forward transmission coefficients of the D-TSVs made of Cu and carbon nanotubes are characterized and compared under different settings of frequencies and temperatures. [ABSTRACT FROM PUBLISHER]

In 2-D van der Waals heterostructures, interactions between atomic layers dramatically change the vibrational properties of the hybrid system and demonstrate several interesting phenomena that are absent in individual materials. In this paper, we have investigated the vibrational properties of the heterostructure between transition metal dichalcogenide (TMD) and hexagonal boron nitride (hBN) on gold film at low- and high-frequency ranges by Raman spectroscopy. Nineteen Raman modes have been observed from the sample, including a new interlayer coupling mode at 28.8 cm−1. Compared to reported experimental results of tungsten disulfide (WS2) on SiO2/Si substrates, the Raman spectrum for WS2 on hBN/Au emerges a blue shift of about 8 cm−1. Furthermore, a remarkable enhancement of Raman intensity can be obtained when tuning hBN thickness in the heterostructure. Through systematic first-principles calculations, numerical simulations, and analytical calculations, we find that the 28.8 cm−1 mode originates from the shearing motion between monolayer TMD and hBN layers. In addition, the gold substrate and hBN layers form an optical cavity and the cavity interference effects enhance the obtained Raman intensity. This paper demonstrates the novel vibrational modes of 2-D van der Waals heterostructure as an effective tool to characterize a variety of such heterostructures and reveals a new method to enhance the Raman response of 2-D materials. [ABSTRACT FROM AUTHOR]

This paper presents the study of the chopper-stabilized magnetic field effect transistor (CHOPFET), a high-resolution silicon magnetic transducer. After a full description of its structure and operating principle, a 3-D multiphysics model is proposed. This model combines the electrical model of conventional silicon electronic devices (i.e., transistors) and the magnetic model in order to obtain accurate transduction effect prediction. Experimental results collected from a set of CHOPFET transducers fabricated in AMS $0.35~\mu \text{m}$ standard CMOS technology effortlessly match the simulations performed on the same process. Analysis and discussions reveal one key result: when the CHOPFET is appropriately biased, its channel current, ${I}_{\text {DS}}$ , can be lowered without magnetic sensitivity loss, i.e., the CHOPFET can achieve high-resolution performance even when operated in a low-power mode. [ABSTRACT FROM AUTHOR]

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ($\gamma $) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption. [ABSTRACT FROM AUTHOR]

Selective laser annealing system was developed to realize fabrications of low-temperature poly-Si thin-film transistors (TFTs) even for large substrate, while the conventional excimer laser annealing system has the limitation in substrate size due to the difficulty in obtaining uniform beam line. In this paper, this new system was applied to fabricate poly-Si TFTs, using two laser exposure methods such as the static exposure and the scan exposure. Grain size increased as the laser energy density increased, and TFTs with the field-effect mobility larger than 100 cm2V−1s−1 with the ON– OFF ratio of drain current of approximately 106 could be obtained. Furthermore, for the scan exposure, periodic grain structure was observed resulting from the lateral solidification. In this condition, variations of electrical properties of TFT could be reduced compared to the case of the static exposure. [ABSTRACT FROM AUTHOR]

This paper reports the process integration and fabrication characteristics of a vertical thin poly-Si channel (VTPC) transfer gate (TG) pixel, which is one of the candidates for future 3-D CMOS image sensor (CIS) applications. The proposed process integration can effectively suppress grain boundary formation at the interface between the photodiode and the poly-Si channel by solid phase epitaxial growth (SPEG) mechanism. Furthermore, dopant diffusion characteristics for source–drain junction formation in poly-Si substrates are investigated using secondary ion mass spectroscopy (SIMS) depth profiles under various process conditions. In addition, combining SIMS results with ${I}_{d}$ – ${V}_{g}$ curve and scanning spreading resistance microscopy measurements, we explained the discrepancy in diffusion characteristics between the bulk and the thin-film poly-Si. Finally, by using optimized SPEG conditions and adopting the proposed VTPC-TG pixel structures in a commercial 5-Mpixel CIS image sensor product, we successfully verified the improvement in image quality. [ABSTRACT FROM AUTHOR]