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This paper investigates the impacts of typical semiconductor material properties—electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core–shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core–shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications. [ABSTRACT FROM PUBLISHER]

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A comprehensive review of modeling techniques and previous models was carried out aiming to remark the originality of the new proposed technique. Once established that SET is a nonlinear system, five classes of nonlinear models were simulated and compared to each other. Characteristic SET curves obtained using Simulation of Nanostructures were used as benchmark. The mean squared error (mse) was used as metric, and the simulation time was computed for each model. Regarding these two criteria—least mse and least simulation time—the Hammerstein–Wiener model outperformed the others models. [ABSTRACT FROM AUTHOR]

The field-plate (FP) technique suppresses the electric field crowding at the p-n junction by inducing the interface charges in the drift region. However, due to the modeling difficulty, the physical meaning cannot be elaborated via the conventional 2-D methods, not to mention the designing optimization. Therefore, the FP assistant reduced surface field effective concentration profile (ECP) is proposed in this paper to explore the physical insight of the FP assistant 2-D coupling. The ECP simplifies the sophisticated 2-D coupling by equating the FP assistant effect to the variation of the ECP. As a result, a simple and effective 1-D analytical model is presented to qualitatively and quantitatively explore the FP-induced surface field reshaping and its distinctive breakdown mechanism. The analytical solutions are found out to be consistent with the simulation results obtained from MEDICI, a commercial TCAD tool. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd. [ABSTRACT FROM AUTHOR]

The layout-induced cylindrical breakdown may occur as a result of the multifinger or circular layout-induced 3-D curvature effect resulting in the breakdown voltage reduction of the power device significantly. In this paper, by using effective doping concentration (EDC) concept, the inherent 3-D problem is simplified as a 1-D problem. Based on the EDC concept, a 1-D analytical model is presented to qualitatively and quantitatively explore the impact of curvature effect on the breakdown mechanism of SOI lateral double diffused MOS. The analytical solutions are found out to be consistent with the simulation results well obtained from MEDICI, a commercial technology computer-aided design tool. To the best of our knowledge, the proposed model is the first 1-D model which can accurately describe the 3-D curvature effect. [ABSTRACT FROM AUTHOR]

In this paper, an analytic model is proposed, which provides, in a continuous manner, the current–voltage ( $I$ – $V$ ) characteristic of high-performance tunneling FETs (TFETs) based on direct bandgap semiconductors. The model provides the closed-form expressions for $I$ – $V$ based on: 1) a modified version of the well-known Fowler–Nordheim (FN) formula (in the ON-state) and 2) an equation that describes the OFF-state performance while providing continuity at the ON/OFF threshold by means of a term introduced as the continuity factor. It is shown that the traditional approaches, such as FN, are accurate in TFETs only through correct evaluation of the total band bending distance and the tunneling effective mass. General expressions for these two key parameters are provided. Moreover, it is demonstrated that the tunneling effective mass captures both the ellipticity of evanescent states and the dual (electron/hole) behavior of the tunneling carriers, and it is further shown that such a concept is even applicable to semiconductors with nontrivial energy dispersion. Ultimately, it is found that the $I$ – $V$ characteristics obtained by using this model are in close agreement with the state-of-the-art quantum transport simulations both in the ON- and OFF-state, thus providing the validation of the analytic approach. [ABSTRACT FROM PUBLISHER]

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( R \mathrm{\scriptscriptstyle ON,\mathsf {sp}} ) decreases from 142.9 to 48.2 \textm\Omega \cdot \mathsf cm^\mathsf 2 , and the gate–drain charge ( Q {\mathsf {gd}} ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

The overall purpose of this paper is the prediction of the ultimate electrical high-frequency performance potential for SiGe C HBTs under the constraints of practical applications. This goal is achieved by utilizing advanced device simulation tools with parameters calibrated to experimental results of most advanced existing technologies. In addition, detailed electrostatic and electrothermal simulations are performed for determining the parasitic capacitances, temperature increase, and safe operating area of aggressively scaled devices. The important figures of merit are then determined from circuit simulation employing an accurate compact model incorporating all relevant physical effects. Based on the vertical profile found in Part I, this paper focuses on achieving a balanced device design by lateral scaling. It is shown that the peak values of (fT, f\max) around (1, 1.5) THz may be achievable. Such a performance limit provides still significant headroom for further developing existing processes and makes SiGe C HBTs well-suitable for highly integrated millimeter-wave applications operating within the low-end of the terahertz gap. [ABSTRACT FROM PUBLISHER]

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology. [ABSTRACT FROM AUTHOR]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]

To simulate semiconductor devices and circuits working at high frequencies or under a large signal input and to better understand their physical effects, a physically based simulation method is proposed in this paper. It utilizes a physical-model-based field simulation to analyze the semiconductor devices in a circuit and incorporates the field simulation into an equivalent-model-based circuit simulation to simulate the circuit. For the field simulation, a genetic-algorithm-based curve-fitting approach is proposed to extract the parameters of the semiconductor devices’ physical models. The proposed method is employed for the analysis of a few circuits containing a commercial p-i-n diode with model number mot_bal99lt1. The feasibility and accuracy of the proposed method are validated through a comparison of its simulation results with the measurement data, and good agreement is observed. The other merits of the proposed method are also illustrated, including its ability to provide useful physical mechanisms for the better understanding of the behavior of the p-i-n diode under various working conditions. [ABSTRACT FROM PUBLISHER]

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results. [ABSTRACT FROM AUTHOR]

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in one-subband approximation and carrier degeneracy. The knowledge of barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time, we also obtain an estimate of the backscattering ratio and the saturation inversion charge. With respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge, which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate lengths down to 70 nm. Moreover, we propose an extension of the backscattering model to the case of 2-D geometries (e.g., bulk MOSFETs). We found that, in this case, backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1-D approach can be significantly different from the real 2-D value. [ABSTRACT FROM AUTHOR]

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell. [ABSTRACT FROM AUTHOR]

We propose a new modeling approach based on the impedance field method (IFM) to analyze the general geometric variations in device simulations. Compared with the direct modeling of multiple variational devices, the proposed geometric variation (GV) model shows a better efficiency thanks to its IFM-based nature. Compared with the existing random geometric fluctuation (RGF) model where the noise sources are limited to the interfaces, the present GV model provides better accuracy and wider application areas as it transforms the geometric variation into global mesh deformation and computes the noise sources induced by the geometric variation in the whole simulation domain. GV model also provides great insights into the device by providing the effective noise sources, equationwise contributions, and sensitivity maps that are useful for device characterization and optimization. [ABSTRACT FROM AUTHOR]

In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations. [ABSTRACT FROM PUBLISHER]

This paper presents a nanotechnology-based high-power-density and low-power-loss on-chip power inductor for dc–dc switching power converters. This power inductor utilizes a composite of bundled multiwalled (concentric) carbon nanotubes (BMWCNTs) and Fe (iron) in order to achieve high performance in a small size. Titanium (Ti) is then added as a coating material on the BMWCNT-based power inductor. The BMWCNT-based power inductor with a single layer and three turns occupies an area of \200\ \mu\m \times \200\ \mu\m. It exhibits an inductance of 206 nH, a quality factor of 427 at 20 MHz, and a dc rated current of 100 mA. The power inductor size and the performance characteristics are competitive with state-of-the-art power inductors. The design, analysis, modeling, and simulation results of the BMWCNT-based power inductor are presented and compared with state-of-the-art conventional power inductors from the literature. [ABSTRACT FROM AUTHOR]

An electric molecular dynamics (MD) method is proposed, where an electroheat solver is introduced into a traditional MD simulation to perform a coupled calculation. The switching mechanism of carbon-based resistive random access memory is studied through this method, and the heat generation and propagation driven by an electric current pulse are simulated during the switching process. Graphitic filament breakage and growth are responsible for resistance switching. The simulation shows that a short and strong voltage pulse induces graphitic filament breakage, resulting in a high-resistance state, whereas a moderate but much longer pulse is required to enable filament growth, resulting in a low-resistance state. Key factors such as the bias condition and the power supply for such switching process are also studied. The results are quantitatively consistent with experimental measurements. [ABSTRACT FROM AUTHOR]

We present a nonlocal history-dependent model for impact ionization gain and noise in avalanche photodiodes (APDs) especially suited for staircase APDs. The model uses a simple energy balance equation to define effective electric fields valid also in the presence of band discontinuities which are then used to express the ionization coefficients. The model parameters have been calibrated against literature data for gain and noise in GaAs and AlxGa1−xAs $({x} = {0.2}, {0.6}, {0.8})$ p-i-n diodes. Application to the experimental data for gain and noise in heterojunction and staircase separate absorption and multiplication APDs is reported to demonstrate the ability of the model in describing complex APD structures. It is found that, in spite of conduction band discontinuities being much larger than valence band ones, hole impact ionization contributes a significant degradation of the noise metrics in GaAs/AlGaAs staircase APDs. These nontrivial insights demonstrate the usefulness of the model to steer device design and optimization. [ABSTRACT FROM AUTHOR]

A method of simulating metallic-island single electron transistors (SETs) and small circuits which speeds up the design-fabrication-characterization cycle is proposed. The method combines finite-elements method to extract device capacitance matrix and standard master equations solved by Monte Carlo to simulate device transport characteristics based on the fabrication geometry and materials. It allows simulation of SET circuits. The simulation method is detailed using two capacitively coupled SETs acting either as an electron box or a sensor. The method is also compared with isolated SETs fabricated using the nanodamascene process and characterized at low temperatures. Experimental devices show clear Coulomb blockade diamonds at 1.5 K and charging energies up to 3 meV. The simulation platform predicts the electrical behavior accurately with minimal fitting parameters. This method allows rapid and accurate design iterations before costly fabrication. [ABSTRACT FROM AUTHOR]

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C–V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi–Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance ( C\mathsf {it} ) is implemented using a common model for systems like Si and Ge. A more complex C\mathsf {it} model is also implemented for III–Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density ( D\mathsf {it} ). [ABSTRACT FROM PUBLISHER]

Recently proposed perturbation analysis and reciprocity relations in photovoltaic conversion are demonstrated in 2-D simulations. The main parameters discussed are the current-conversion efficiency, which enables accurate calculation of the sensitivity of maximum power to different recombination parameters, and its derived local series resistance, whose weighted average is exactly equal to the series resistance obtained by the double illumination method. Both parameters can be displayed as spatial maps to visually aid multidimensional computer simulations. Finally, the suitability of mapping the local series resistance from luminescence images is discussed with the help of simulated examples. The experimental and computational procedures to generate these maps are among the easiest proposed so far in the literature and require no ad hoc assumptions. [ABSTRACT FROM AUTHOR]

A new relaxation-time-approximation-based nonquasi-static (NQS) MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static description of the MOSFET. The model is implemented in two widely used circuit simulators and is tested for speed and convergence. It is verified by comparison with technology computer-aided design simulations and experimental data and by application of a recently developed benchmark test for NQS MOSFET models. [ABSTRACT FROM PUBLISHER]

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap-to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation. [ABSTRACT FROM PUBLISHER]

A new approach to the analytical solution of the 2-D Poisson equation including the inversion-charge density in undoped square gate-all-around metal–oxide–semiconductor field-effect transistors has been developed. We have obtained functions with different degrees of complexity to calculate the electric potential in the devices under study. The results obtained are compared with the data simulated by solving the Poisson equation numerically. A good fit is achieved both for the electric potential and the inversion charge, which are calculated by means of Gauss's law. [ABSTRACT FROM PUBLISHER]

The electron-transport processes in a low-barrier Mott diode are studied by the methods of numerical simulation. The effects related to the quasi-ballistic motion of electrons are examined. The I–V characteristics of the diode are obtained. We have performed a comparative analysis of the results of the simulation, which was carried out using different approaches: the Monte Carlo method and the local-field model. The calculated I–V characteristics are compared with the experimental dependence. The applicability limits of the approaches we used are analyzed. [ABSTRACT FROM PUBLISHER]

A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating. [ABSTRACT FROM AUTHOR]

Analytical expressions for terminal charges of an independent-gate asymmetric double gate MOSFET (DGFET) are derived. The new charge model is Cinfin continuous, valid for all bias conditions and does not involve charge-sheet approximation. This is accomplished by developing the symmetric linearization method in the form that does not require identical boundary conditions at the two Si--SiO2 interfaces and allows for the volume inversion in the DGFET channel. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The terminal charges expressions are similar to those in the PSP bulk MOSFET model and in the PSP-based common-gate symmetric DGFET model. The latter becomes a special case of the new model. [ABSTRACT FROM AUTHOR]

A TCAD-oriented mobility model, whose main features are: 1) inclusion of ballistic effects in the linear region and 2) smooth transition between the linear and saturation regions, is presented. It is applied to short-channel double-gate thin-body InGaAs MOSFETs. The bases of the model are the concept of ballistic mobility and Matthiessen's rule in the linear regime, and the saturation velocity within a modified Canali model at high-longitudinal fields. Comparisons with accurate semiclassical multivalley multisubband Monte Carlo transport simulations indicate that TCAD simulations making use of the proposed model are able to correctly predict the terminal currents and the internal device quantities in the linear regime in a 15-nm device with no need of fitting parameters. In the saturation region, an empirical adjustment of the saturation velocity is needed, after which currents are accurately predicted for a wide range of gate lengths and bias conditions. [ABSTRACT FROM AUTHOR]

Surface-potential-based drain current model is presented for amorphous InGaZnO thin-film transistors considering both exponential deep and tail trap states densities in the energy gap. The trap states densities are determined by the numerical calculation on the basis of the assumption that the trapped carrier concentration is much higher than the free carrier concentration. The analytical drain current model is developed consistent with the numerical calculation, and verified by the experimental data at different temperatures. [ABSTRACT FROM PUBLISHER]

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance. [ABSTRACT FROM AUTHOR]

A novel cosimulation algorithm that combines physical-model-based multiphysics simulation with equivalent-model-based circuit simulation is proposed. In the algorithm, multiphysics simulation couples multiple physical equations (e.g., the electromagnetic, semiconductor transport, thermodynamics equations, etc.) to be solved numerically by an iterative approach. The multiphysics simulation is for modeling the electrothermal behavior of semiconductor devices, and then, it is incorporated into the circuit simulation to extend the simulation from semiconductor devices to circuits. Employing the proposed algorithm, sample numerical results for the temperature effect on circuits comprising commercial p-type–intrinsic–n-type diodes with a model number of mot_bal99lt1 are obtained and compared to measurement data. The comparison shows a good agreement between these two sets of data, which validates the feasibility and accuracy of the proposed algorithm. Moreover, the proposed algorithm can provide a useful physical mechanism for understanding temperature effect on semiconductor devices and circuits. [ABSTRACT FROM PUBLISHER]

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools. [ABSTRACT FROM PUBLISHER]

We propose a behavioral circuit model to precisely predict optical responses of an active-matrix liquid crystal (LC) display (LCD) using a patterned vertical alignment (PVA) mode. To get more accurate simulation results, we propose two LC groups with different time constants for a pixel after observing the LCD pixels by using a high-speed camera. In addition, we include a time-delay concept into our behavioral model for brightening or rising transitions. We describe the behavior of the PVA-LCD by using the analog hardware description language Verilog-A. We simulate the PVA-LCD panel by importing the behavioral circuit model in the circuit simulator SmartSPICE. The simulation results of the transient optical responses show excellent matches with the measurement ones. [ABSTRACT FROM PUBLISHER]

Two compact models for single-electron memory (SEM) are proposed and validated by comparisons with the program SIMON. The approach is based on the master equation method and the orthodox theory. The specific and efficient algorithms for each model are presented. The first model is static and allows directly calculating the final number of electrons on the memory dot. The second model is dynamic, which evaluates every electron tunnel event to assess the stored charge variation and determines the writing or retention times. Both static and dynamic models are written in Verilog-A language and implemented in IC design framework. These SEM models are attractive for circuit simulation to find out the optimal biasing strategy and memory architecture. [ABSTRACT FROM PUBLISHER]

We present a compact model to calculate the capacitance of undoped high-mobility low-density-of-states materials in double-gate device architecture. Analytical equations for estimating the subband energies, while taking the effect of wavefunction penetration into the gate oxide and the effective mass discontinuity, are presented for the first time in a compact modeling framework. The surface potential equation for a two subband system is solved, assuming Fermi–Dirac statistics, and compared to numerical Schrodinger–Poisson simulations. The importance of accurately treating the charge profile distribution is illustrated, and an analytical expression for the effective oxide thickness to model the charge centroid is developed. [ABSTRACT FROM AUTHOR]

A 3-D simulator of semiconducting nanocrystal (NC)-based single-electron transistors (SETs) is presented. It is based on the self-consistent solution of Poisson and Schrödinger equations. The resulting wave functions are used to compute the bias-dependent tunneling rates in the weak dot-to-lead coupling limit. These rates are used as input data of a Monte Carlo code, which treats the sequential transport of electrons through the tunnel barriers. The simulator is applied to a typical silicon-NC SET. The resulting current–voltage characteristics are discussed in terms of tunneling rates, chemical potentials, and wave functions. The influence of all device parameters and of the temperature are carefully analyzed. [ABSTRACT FROM AUTHOR]

This brief presents a novel scaling theory for fully depleted, multiple-gate (MG) MOSFET. The scaling theory is derived from the equation for effective number of gates (ENGs), ENGQG=ENGDG,1+ENGDG,2 where the MG device can be genuinely broken into two equivalent double-gate (DG) transistors working in parallel based on the perimeter-weighted-sum method. Numerical device simulation data for drain-induced-barrier-lowering were compared with the model to validate the formula. Using the scaling theory, the minimum effective channel length improvement factor of \rhoMG=1-(\rm ENGDG/\rm ENGMG)^1/2 shows an improvement of up to 30% in the minimum effective channel length for the MG MOSFET in comparison with DG MOSFET. [ABSTRACT FROM PUBLISHER]