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In this article, the impacts of read operation under transient gate voltage sweep on the memory window (MW) of ferroelectric field-effect transistor (FeFET) are systematically investigated. By taking into consideration the polarization switching dynamics, it reveals a significant dependence on the sweep range and rate of gate voltage. With increasing sweep range, the increase of polarization switching leads to the monotonically increasing MW. However, different from sweep range, the MW of FeFET nonmonotonically varies with the increasing sweep rate, which is caused by the competition between decreased polarization switching and increased voltage drop on ferroelectric (FE) layer during forward sweep. Besides, compared with the MW obtained by pulsed gate voltage, it is found that the MW obtained by swept gate voltage can be the smaller one even without the consideration of charge trapping contribution. Furthermore, the impacts of FE switching time on MW are also discussed, indicating that the MW may not always be a constant even under quasi-static sweeping with low sweep rate, and the relationship between sweep rate of gate voltage and switching speed of FE plays a critical role in MW evaluation. [ABSTRACT FROM AUTHOR]

In this work, utilizing the unique features of conventional Si-based tunnel FET (TFET), a TFET-based leaky integrate-and-fire (LIF) neuron with higher energy efficiency and reduced hardware cost is proposed. Compared with traditional CMOS-based LIF neuron, the proposed TFET-based LIF neuron can produce an additional bio-plausible after-hyperpolarization (AHP) behavior and relative refractory period without extra hardware cost by exploiting the features of large Miller effect and forward p-i-n current in TFET. Moreover, the typical ambipolar effect and superlinear onset behaviors in conventional Si-based TFET enable the lower hardware cost and lower energy consumption ($\sim 10\times $ reduction) for TFET-based neuron. Furthermore, the proposed TFET neuron-based spiking neural network (SNN) is demonstrated for pattern recognition tasks, showing its advantage of significant energy efficiency. This work provides a promising highly integrated and energy-efficient solution for the hardware implementation of spiking neuron for neuromorphic computing. [ABSTRACT FROM AUTHOR]

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal–ferroelectric–insulator–semiconductor (MFIS) structure is presented in this work. With a damping parameter ρ in the Landau–Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues. [ABSTRACT FROM AUTHOR]

We propose two different designs of p-type piezoelectric (PE) FinFETs (PE-FinFETs) covering low-power (LP) and high-performance (HP) operation modes. LP mode PE-FinFETs achieve a lower OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) and HP mode PE-FinFETs result in a larger ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$). These two different modes are achieved by simply changing the outer PE-gates bias. The advanced nonequilibrium Green’s function (NEGF) approach self-consistent with six-band ${k}\cdot {p}$ method including phonon scattering is used to investigate the device performance. The gate voltage-controlled strain is analytically derived from the principle of PE effect. The HP and LP PE-FinFETs are studied, respectively, and the impacts of channel material, device orientation, and phonon scattering on both HP and LP PE-FinFETs are comprehensively investigated. The simulation results show that Ge is superior to Si for both LP and HP PE-FinFETs. With a supply voltage of 0.5 V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ of Ge LP mode PE-FinFETs is reduced by 18 times, and Ge HP mode PE-FinFETs obtain 50% ON-current enhancement. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is unchanged for LP (HP) mode PE-FinFETs. Phonon scattering not only causes a large ${I}_{ \mathrm{\scriptscriptstyle ON}}$ degradation but also changes the optimal device orientation for both Si and Ge HP mode PE-FinFETs compared to their counterparts without phonon scattering. [ABSTRACT FROM AUTHOR]

Energy efficiency has become the main concern of IC technology. Tunnel FET (TFET) is recognized to possess the superiority of energy efficiency over MOSFET at ultralow voltage, while variability might limit the voltage reduction and thus the energy saving. Recently, device source doping gradient (SDG) is found to be the dominant variation source in TFET. In this paper, for the first time, with the awareness of SDG variation, the energy efficiency of TFET-based circuits with different activity factors ( $\alpha $ ) is comprehensively reassessed and the device optimization strategy is provided. It is found that the superiority of energy efficiency of TFET will significantly decrease especially for the more active circuit due to the inherent tradeoff between SDG variation and nominal SDG. Based on the quantitative relationship between SDG variation and nominal SDG extracted from the experimental devices, the optimal design of tunnel junction abruptness to maximize the circuit energy efficiency is obtained, leading to significant energy efficiency improvements of TFET-based circuit over MOSFET even for circuit with high $\alpha $. This paper provides helpful device design guidelines for TFET with device variability awareness from the perspective of circuit energy efficiency. [ABSTRACT FROM AUTHOR]

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( \textN\text {S}) and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance. [ABSTRACT FROM PUBLISHER]

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band tunneling efficiency, the underlying layer of HS-TFET could provide extra drain current increment with increasing gate voltage, and thus effectively improve the subthreshold characteristics for steeper average SS. The simulation results show that the proposed Si–Ge-based HS-TFET can achieve much steeper average SS (25 mV/decade) than conventional Si TFET (42 mV/decade), exhibiting more than one decade higher I60 without leakage current degradation. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET. [ABSTRACT FROM AUTHOR]

In this paper, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET. It is found that the Vth shifts and subthreshold swing (SS) degradation induced by interface traps in TFET and MOSFET have the same trends, but the impacts on $I_{{\rm \scriptstyle ON}}$ are different because of the novel conduction mechanism of TFETs when compared with MOSFETs. Moreover, nTFET is intrinsically more immune (or susceptible) to Vth shift induced by acceptor- (or donor-) type interface traps than nMOSFET. Therefore, reducing the potential degradation induced by the interface traps can be achieved by optimizing the position of CNL. The results indicate that nTFET is more immune to the Vth shift than nMOSFET with CNL below a critical energy. In addition, the trap-induced SS degradation of TFET is severer than MOSFET in electrostatics. Moreover, it is found that the $I_{{\rm \scriptstyle ON}}$ , Vth , and $I_{{\rm \scriptstyle OFF}}$ fluctuations in nMOSFET and nTFET are also dependent on the position of CNL. With CNL below the critical energy, the $I_{{\rm \scriptstyle ON}}$ fluctuation and Vth fluctuation of nTFET are smaller than those of nMOSFET. The results are helpful for the interface optimization of TFETs. [ABSTRACT FROM PUBLISHER]

We thank Prof. Shaker for his interest in the above article and his positive statement in the Comments. Regarding the errors raised by Prof. Shaker, the following are our replies. [ABSTRACT FROM AUTHOR]