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In this article, the impacts of read operation under transient gate voltage sweep on the memory window (MW) of ferroelectric field-effect transistor (FeFET) are systematically investigated. By taking into consideration the polarization switching dynamics, it reveals a significant dependence on the sweep range and rate of gate voltage. With increasing sweep range, the increase of polarization switching leads to the monotonically increasing MW. However, different from sweep range, the MW of FeFET nonmonotonically varies with the increasing sweep rate, which is caused by the competition between decreased polarization switching and increased voltage drop on ferroelectric (FE) layer during forward sweep. Besides, compared with the MW obtained by pulsed gate voltage, it is found that the MW obtained by swept gate voltage can be the smaller one even without the consideration of charge trapping contribution. Furthermore, the impacts of FE switching time on MW are also discussed, indicating that the MW may not always be a constant even under quasi-static sweeping with low sweep rate, and the relationship between sweep rate of gate voltage and switching speed of FE plays a critical role in MW evaluation. [ABSTRACT FROM AUTHOR]

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band tunneling efficiency, the underlying layer of HS-TFET could provide extra drain current increment with increasing gate voltage, and thus effectively improve the subthreshold characteristics for steeper average SS. The simulation results show that the proposed Si–Ge-based HS-TFET can achieve much steeper average SS (25 mV/decade) than conventional Si TFET (42 mV/decade), exhibiting more than one decade higher I60 without leakage current degradation. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET. [ABSTRACT FROM AUTHOR]

We thank Prof. Shaker for his interest in the above article and his positive statement in the Comments. Regarding the errors raised by Prof. Shaker, the following are our replies. [ABSTRACT FROM AUTHOR]