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A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

An analytical model is proposed in this paper for the surface electric field around the drain-side gate edge in the AlGaN/GaN HEMT to which the gate leakage, current collapse, and so on are highly related. Conformal mapping is implemented to mirror the device structure into a simplified geometry and the solution to the Laplace equation is thus achieved. Obtained from the proposed model, the surface electric field in the AlGaN/GaN HEMT shows a high peak around the drain-side gate edge, which is the cause for many reliability issues in HEMTs. The proposed model is then used to study the main factors that may impact the field distribution, such as drain voltage, thickness of barrier, and so on. Numerical simulations are carried out and compared with the analytical model. The high agreement between the results verifies the proposed model. [ABSTRACT FROM AUTHOR]

In this article, the thermally induced threshold voltage (${V}_{\text{TH}}$) shift was investigated on two types of normally- OFF p-GaN gate high-electron-mobility transistors (HEMTs), featuring either an Ohmic-type or a Schottky-type gate. A positive ${V}_{\text{TH}}$ shift in a Schottky-type device and a negative ${V}_{\text{TH}}$ shift in an Ohmic-type device were observed at elevated temperatures. Temperature-dependent gate current–voltage (${I}-{V}$) and the transfer-length-method (TLM) analysis revealed that the bias condition across the p-GaN/AlGaN/GaN heterostructures was changed in both Schottky- and Ohmic-type devices as temperature increased. We propose that: 1) temperature-enhanced hole injection through thermionic emission which lowers the knee voltage of the Ohmic-metal/ p-GaN contact in Ohmic-type devices and 2) thermally enhanced gate current which enlarges the bias voltage across the Schottky-metal/p-GaN junction in Schottky-type devices, resulted in the observed ${V}_{\text{TH}}$ instability characteristics. The photoluminescence measurements were conducted to verify the thermally-enhanced ionization of magnesium dopants in the p-GaN and the corresponding instability issues. [ABSTRACT FROM AUTHOR]