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Energy efficiency has become the main concern of IC technology. Tunnel FET (TFET) is recognized to possess the superiority of energy efficiency over MOSFET at ultralow voltage, while variability might limit the voltage reduction and thus the energy saving. Recently, device source doping gradient (SDG) is found to be the dominant variation source in TFET. In this paper, for the first time, with the awareness of SDG variation, the energy efficiency of TFET-based circuits with different activity factors ( $\alpha $ ) is comprehensively reassessed and the device optimization strategy is provided. It is found that the superiority of energy efficiency of TFET will significantly decrease especially for the more active circuit due to the inherent tradeoff between SDG variation and nominal SDG. Based on the quantitative relationship between SDG variation and nominal SDG extracted from the experimental devices, the optimal design of tunnel junction abruptness to maximize the circuit energy efficiency is obtained, leading to significant energy efficiency improvements of TFET-based circuit over MOSFET even for circuit with high $\alpha $. This paper provides helpful device design guidelines for TFET with device variability awareness from the perspective of circuit energy efficiency. [ABSTRACT FROM AUTHOR]

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( \textN\text {S}) and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance. [ABSTRACT FROM PUBLISHER]

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band tunneling efficiency, the underlying layer of HS-TFET could provide extra drain current increment with increasing gate voltage, and thus effectively improve the subthreshold characteristics for steeper average SS. The simulation results show that the proposed Si–Ge-based HS-TFET can achieve much steeper average SS (25 mV/decade) than conventional Si TFET (42 mV/decade), exhibiting more than one decade higher I60 without leakage current degradation. [ABSTRACT FROM PUBLISHER]

In this work, utilizing the unique features of conventional Si-based tunnel FET (TFET), a TFET-based leaky integrate-and-fire (LIF) neuron with higher energy efficiency and reduced hardware cost is proposed. Compared with traditional CMOS-based LIF neuron, the proposed TFET-based LIF neuron can produce an additional bio-plausible after-hyperpolarization (AHP) behavior and relative refractory period without extra hardware cost by exploiting the features of large Miller effect and forward p-i-n current in TFET. Moreover, the typical ambipolar effect and superlinear onset behaviors in conventional Si-based TFET enable the lower hardware cost and lower energy consumption ($\sim 10\times $ reduction) for TFET-based neuron. Furthermore, the proposed TFET neuron-based spiking neural network (SNN) is demonstrated for pattern recognition tasks, showing its advantage of significant energy efficiency. This work provides a promising highly integrated and energy-efficient solution for the hardware implementation of spiking neuron for neuromorphic computing. [ABSTRACT FROM AUTHOR]

We thank Prof. Shaker for his interest in the above article and his positive statement in the Comments. Regarding the errors raised by Prof. Shaker, the following are our replies. [ABSTRACT FROM AUTHOR]