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We extract an AlGaN surface state spectrum with a density ( ${D}_{\text{SS}}$ ) ranging between $1.4\times10$ 12 and $4.7\times10$ 12 eV−1cm−2. The low ${D}_{\text{SS}}$ is achieved with in situ SiN passivation. ${D}_{\text{SS}}$ is extracted from ungated AlGaN/AlN/GaN heterostructures with varied AlN thicknesses between 0 and 2 nm: increased AlN thicknesses in heterostructures monotonously increase two-dimensional electron gas (2DEG) densities ${N}_{\text{sh}}$ and AlGaN surface potential energies ${q} {\varphi } _{\text{s}}$ , and ${D}_{\text{SS}}$ is extracted with $\boldsymbol {\Delta } {N}_{\text{sh}}$ – $\boldsymbol {\Delta } {\varphi }_{\text{s}}$ correlations. The ${D}_{\text{SS}}$ extraction methodology in this work features calibrated polarization charge values, Hartree approximation-based 2DEG profile calculation, and incorporated C-doped GaN (C-GaN) substrate impact on 2DEG. We also extract the charge neutrality level at the AlGaN surface, which is ~0.95 eV below conduction band minimum.

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and ${f}_{\text {MAX}}$ of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process leads to ${f}_{\text {MAX}}$ enhancement up to ~50% for devices scaled down to 0.32- $\mu \text{m}$ gate lengths. The gate resistance for the T-shaped gate is modeled from the S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and the parasitic capacitance in GaN HEMTs is highlighted in this case.

The basic analog parameters of three splits of In x Ga1– x As nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO2/1-nm Al2O3 gate. The low equivalent oxide thickness improves the electrostatic coupling, enhancing ${I}_{{\text {DS}}}$ , and, consequently, also gm and ${A}_{V}$ , especially for higher $\text {V}_{{\text {GS}}}$ . The InGaAs tunnel field-effect transistors (TFETs) show compatible performance with Si TFETs, and have better performance than Si MOSFETs, making them useful for low-power and low-voltage analog applications. The highest efficiency is found using the combination of a 2-nm HfO2 with In0.53Ga0.47As, due to the 56-mV/dec subthreshold swing obtained. For all splits, the ${A}_{V}$ peak can be related to the ${V}_{{\text {GS}}}$ necessary for band-to-band tunneling to become the dominant transport mechanism.

A simple analytical low-field electron mobility model to be employed for technology computer-aided design of thin-body MOSFETs based on III-V compound semiconductors is presented. The scattering sources accounted for in the model are Coulomb centers, lattice vibrations (i.e., phonons), and surface roughness. The dependence of the thin-body effective thickness on the transverse electric field is calculated through 1-D Schrodinger–Poisson numerical simulations and is introduced in the model by means of an appropriate analytical function. Then, the free-electron density distribution is determined by considering both quantization effects and oxide–semiconductor interface traps. The model is calibrated on the experimental data collected on In0.53Ga0.47As-on-InP thin-body MOSFETs featuring body thicknesses as low as 5 nm. In particular, the model accurately reproduces $C_{G}$ – $V_{\mathrm{ GS}}$ characteristics, effective mobility against inversion layer charge plots, and $I_{\mathrm{ DS}}$ – $V_{\mathrm{ GS}}$ curves at low $V_{\mathrm{ DS}}$ .

This correspondence highlights that the Gibbs free energy description of a ferroelectric capacitor in series with a paraelectric capacitor, depends on the initial charge on the plates of the ferroelectric capacitor. An incomplete Gibbs free energy description, as in the original manuscript, leads to an incorrect simulation result. Therefore, a fully comprehensive analytical description and a corrected conclusion concerning the particular point of an increase in apparent coercive voltage in the steep-slope ferroelectric tunnel-FET, are presented.

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection.

The steep-slope ferroelectric tunnel-FET (SS-FeTFET), consisting of an InGaAs TFET with a sub-60 mV/dec subthreshold swing (SS) at room temperature and an externally connected high-quality single-crystalline PZT capacitor, displays improved SS compared to the standalone TFET. In this article, we describe the measurement procedure and measurement results of this SS-FeTFET in great detail. To quantitatively extract the ferroelectric (FE) polarization during voltage sweeps, device simulations of the TFET are combined with the SS-FeTFET measurement results. Finally, qualitative insight in some peculiarities of the experimental observations is given, such as the apparent coercive voltage that is larger in the SS-FeTFET than in the standalone FE, the shape of the polarization during voltage sweeps, and the small polarization hysteresis loop at voltages close to the apparent coercive voltage.