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In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation. [ABSTRACT FROM AUTHOR]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]

In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors. [ABSTRACT FROM AUTHOR]

We present a self-consistent 2-D quantum-mechanical model for charge distribution in cylindrical gate-all-around devices with computation of the gate tunneling current. The validity of 1-D approximations for the charge and the gate current is discussed, assessing the validity of a previously proposed analytical approximation for the tunneling current in the Fowler-Nordheim regime. [ABSTRACT FROM PUBLISHER]

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology. [ABSTRACT FROM AUTHOR]