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A drain-extended (De) FinFET (DeFinFET) with a high-k dielectric field plate is proposed for high-voltage (HV) system-on-chip (SoC) applications at 10-nm CMOS technology nodes. Conventional DeFinFETs without the dielectric field plate and DeFinFETs with SiO2 and HfiO2 field plate are investigated by varying the length (LEXT) and the doping concentration (NEXT) of the fin extension and the thickness (TFOX) of the dielectric field plate. The optimized device with the HfiO2 field plate has a high breakdown voltage (VBD) of 8.56 V, a low specific ON-state resistance (RON_sp) of 6.40Ω ⋅ μm2, and a large figure of merit (VBD2/RON_sp) of 11.46 W/ $μm2, which are greatly improved HV performance over other devices. This indicates that the HfiO2 field plate can effectively address the tradeoff between VBD and RON_sp. In addition, the excellent electrical characteristics such as high ON-state current (ION) of 3.07 × 10-4 A/μm, low OFF-state current (IOFF) of 6.54\times 10-10 A/μm, and small subthreshold swing (SS) of 65.54 mV/decade are observed for the optimized HfiO2-DeFinFET. Consequently, the proposed design with the high-k field plate can be a pathway to realize HV DeFinFETs for SoC technology. [ABSTRACT FROM AUTHOR]

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height ( H\textrm {fin} ) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I – V/C – V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the . On the other hand, the RC delay mostly decreased due to greater ON-current as the H\textrm fin increased. The RC delay with different power supply voltages ( V\textrm {DD} = 0.55 and 0.75 V) was also studied to see the effect of V\textrm {DD} scaling. Finally, a selective deposition was suggested to improve the $RC$ delay about 13%. [ABSTRACT FROM PUBLISHER]

We investigate the effect of single grain boundary (SGB) with arbitrary angles on the threshold voltage ( \(V_{\rm {th}}\) ) variation in sub-50-nm polysilicon (poly-Si) channel devices using 3-D simulation. An SGB in the poly-Si channel causes changes in potential barrier profile resulting in the variation of \(V_{\rm {th}}\) . As the planar devices scale down to 20-nm, oblique SGB can significantly increase the whole potential barrier profile and cause large \(V_{\rm {th}}\) variation. However, due to superior gate controllability, the gate-all-around devices show relatively small increase of the conduction energy band, and thus mitigate the \(V_{\rm {th}}\) variation even in 20-nm poly-Si channel. [ABSTRACT FROM AUTHOR]