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The article explains the technology involved in the dual-threshold-voltage ([V.sub.T]) transistor design, which is used in the sub-100-nm technology nodes. The technique is shown to be extremely advantageous because yields lower dynamics power consumption and lower performance penalty, as compared to the other devices.

A design methodology for optimizing low-temperature poly-Si (LTPS) thin-film transistors (TFTs) for digital super and subthreshold operations is presented. The optimization of LTPS TFTs results in the achievement of comparable performance as a single-crystalline silicon silicon-on-insulator (SOI).

The article describes about an analytical model for computing the potential distribution in gate underlap double-gate symmetric MOS transistors.

A methodology for modeling and optimizing FinFET devices for robust and low-power SRAMs is discussed. There is 65 percent reduction in SRAM cell leakage and improvement in cell read-failure probability due to the optimization of spacer thickness.

The impact of gate underlap on the effective gate capacitance of double-gate MOS (DGMOS) transistor for digital-subthreshold operation is analyzed. It is seen that, with optimum gate underlap, the parasitic fringe capacitances of DGMOS can be significantly reduced resulting in higher performances and lower power consumption.

The advantages of using asymmetric halo MOSFETS over conventional symmetric halo MOSFETS to minimize static seepage in sub-50-nm CMOS circuits, are emphasized. Improved performance is observed in circuits developed with AH transistors due to seepage of less static power.

The impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS transistors is analyzed. The effects of process variation in gate underlap devices are discussed.

Dual-threshold-voltage (VT) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-VT (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-VT technology options--increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness--is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping. [ABSTRACT FROM AUTHOR]