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This paper reports the AlGaN/GaN/ Si $\delta $ -doped AlGaN/GaN:C HEMT device on silicon with high channel conductivity, high breakdown field (E-field) strength, and low current collapse by using the Si-doped AlGaN back barriers. The Si $\delta $ -doped AlGaN back barrier was used to compensate for the reduction of channel conductivity as a result of a carbon-doped semiinsulating GaN buffer layer. The maximum drain current increases from 412 to 720 mA/mm, and peak extrinsic transconductance is improved from 103 to 210 mS/mm. Due to the reduction of electric field between the gate and drain along the GaN channel by inserting the Si $\delta $ -doped AlGaN back barrier layer, it can effectively suppress the capture of electrons in channel by carbon-induced accepted traps in the GaN:C buffer. Combined with the high conductivity of Si $\delta $ -doped AlGaN back barrier and high resistance of GaN:C buffer, the device showed the high breakdown E-field strength and the low specific on-resistance. Our proposed device is observed to hold a gate–drain voltage of 769 V at $\textsf {10}~\mu \text{A}$ /mm (7- $\mu \text{m}$ gate–drain spacing) and 0.53 $\text{m}\Omega ~\cdot $ cm $^{{2}}$ and the gate-to-drain electric field corresponds to 1.1 MV/cm. [ABSTRACT FROM AUTHOR]

In this paper, threshold voltage (${V}_{{\textsf {th}}}$) shift in Al2O3/ AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) induced by charge trapping and the impacts of postmetallization annealing (PMA) were studied. In addition to the transient voltage shift caused by interface trapping effect, retentive voltage shift was also observed which was attributed to border traps with very large emission time constant ($\tau _{e}$). PMA has little influence on the transient ${V}_{\textsf {th}}$ shift which is related to interface traps with $\textsf {18}~\textsf {s}< \tau _{e}< \textsf {54}$ s, while the total interface traps with $\textsf {4}~\textsf {s} < \tau _{e}< \textsf {54}$ s are reduced by PMA from $\textsf {4.03} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$ to $\textsf {1.77} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$. Interface trapping dominates at low program voltage (${V}_{p}$), while border trapping becomes remarkable with ${V}_{p}$ above the critical level. Due to the cumulative border trapping effect, an increase in program voltage by per volt causes an additional retentive voltage shift by about $\textsf {1}$ V. PMA leads to an increase in critical ${V}_{p}$ from 5 to 7 V, which therefore results in a decrease in the density of total accessible border traps from $\textsf {1.99} \times \textsf {10}^{\textsf {13}}\,\,\textsf {cm}^{-\textsf {2}}$ to $9.25\times \textsf {10}^{\textsf {12}}$ cm−2 with ${V}_{p}$ up to 12 V. The border trapping for both devices with and without PMA shows similar retention characteristics, with ${V}_{{\textsf {th}}}$ recovery as small as 1.2 V after one week. [ABSTRACT FROM AUTHOR]