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In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ( \rho c ) of (1.3 – 1.5) \times 10^-9 ~\Omega \cdot \text cm^2 on Si:P. This PCAI + TiSix technique utilizes light amorphization (low-energy implantation), thin Ti and TiSix film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSix-induced \rho c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced \rho c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low \rho c is strongly correlated with the formation of interfacial TiSix crystallites between amorphous TiSi alloy and Si. [ABSTRACT FROM PUBLISHER]

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]