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Indium gallium nitride (InGaN) vertical-cavity surface-emitting lasers (VCSELs) with top dielectric and bottom pipe-gallium nitride (GaN) distributed Bragg reflectors (DBRs) were demonstrated. Pipe-GaN DBR structure consisted of a lateral wet-etched pipe-GaN layer and a GaN layer in the 20 pair stack structure as an embedded reflector. The optical birefringence behavior of the anisotropic pipe-GaN structure induced the polarization properties in the reflectance and electroluminescence (EL) spectra. Polarization EL emission peaks with narrow line-widths were measured at 430.8 nm (perpendicular to pipe-GaN) and 432.5 nm (along with pipe-GaN), respectively. The EL emission peaks with high polarization ratios were observed due to the short resonance cavity effect with the birefringence pipe-GaN DBR structure.

In this work, we report high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with atomic layer deposited Al₂O₃ dielectric processed at a minimal temperature of 189.6 °C via microwave annealing (MWA). The a-IGZO TFT with MWA exhibits an improvement of 57% in subthreshold swing (SS) compared with the unannealed device; meanwhile, it retains high field-effect mobility of up to 29.2 cm²/(V · s) and large switching ratio of >10⁸. Moreover, the SS of the device was further reduced through a two-step MWA treatment. It is believed that MWA treatment effectively reduces the density of trap states associated with oxygen vacancies, promotes the formation of lattice oxygen, and thus improves the quality of IGZO film. MWA with low thermal budget shows great potential in applications of the back-end of line (BEOL)-compatible oxide devices.

The dispersion and dielectric attenuation characteristics of a double-staggered grating waveguide (DSGW) are two crucial features related to the output characteristics of a sheet-beam traveling-wave amplifier and have been previously studied by using theoretical analysis and simulations. In this work, these two characteristics are both experimentally studied. Two ${H}$ -band (220–325 GHz) DSGW circuit prototypes with and without dielectric attenuators made of the BeO-TiO2 composite ceramic were machined by using nanocomputer numerical control milling. Experimental studies of the dispersion property were performed successfully where the measurement results were in good agreement with those predicted by simulations, exhibiting a wide passband of 70 GHz (230–300 GHz). The measured transmission coefficient has been decreased from −5 to −55 dB after the introduction of dielectric attenuators, experimentally verifying the feasibility of the adopted methodology. The effects of the variations of dispersion relation and transmission loss on the beam-wave interaction stability were also investigated.

A high-permittivity (high- ${k}$ ) inserted-oxide FinFET (iFinFET) structure with low-permittivity inner spacers is proposed for CMOS transistor scaling to the 3-nm technology node and beyond. The process to fabricate an iFinFET is similar to the process to fabricate a nanosheet field-effect transistor (NSFET); no additional lithography masks are needed. Unlike the NSFET and the nanowire field-effect transistor (NWFET), which each require significant spacing between the nanosheets or nanowires (NWs) to accommodate metallic gate and dielectric insulator multilayer stacks, the iFinFET requires only a single ultrathin high- ${k}$ inserted-oxide (i-oxide) layer between the NWs, allowing more NWs to be vertically stacked within the constraint of a maximum total channel height. The i-oxide layers serve to allow fringing electric fields from the gate to penetrate into the NWs to achieve improved electrostatic integrity. Simulated performance characteristics of the proposed iFinFET structure are compared against those for the FinFET, NWFET, and NSFET. The iFinFET is projected to achieve the best electrical performance when the footprint (device layout width) is less than 80 nm.

This article presents the design and fabrication results of the silicon carbide (SiC) super-junction Schottky barrier diode (SBD). The impact of two key device structure parameters, i.e., mesa width (MW) and trench width (TW), on the device forward and reverse performance is studied by numeric simulations and measurements. Furthermore, a simple and efficient termination structure, i.e., wide-trench termination, is proposed to protect the device edge. With this termination, the simulated device breakdown voltage is significantly increased from 1423 to 2600 V with a wide-trench termination width (WTW) larger than $20~\mu \text{m}$ . The outermost MW (OMW) of the transition region is also investigated. It is found that the narrower OMW can mitigate the electric field crowding at the top of the outermost mesa and reduce the electrical stress of the dielectric. Devices with different structural parameters are fabricated and measured. The device with WTW $= 50\,\,\mu \text{m}$ and the optimum OMW demonstrates the highest breakdown voltage of 1920 V. The specific ON-resistance ( ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ ) of this device is 1.6 $\text{m}\Omega \cdot $ cm2. Subtracting the substrate resistance, the ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ is only 1.2 $\text{m}\Omega \cdot $ cm2. Such device performance successfully breaks the theoretical 1-D limit of the SiC unipolar device. Furthermore, the leakage current path of the fabricated device is investigated by thermal emission microscope (EMMI). Future improvements to reduce the leakage current are also provided.

In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO 2, and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance—a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from Sentaurus 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

The operation speed of dynamic random access memory devices has been increasing with respect to the evolution of electronic devices. This in turn has induced a decrease in the allowed time for the operation. Therefore, the effective capacitance degradation in which the capacitance gradually decreases with increasing frequency of applied ac voltage is a severe concern for decreasing capacitance during fast operation, in addition to inducing reliability degradation. Hence, in this article, the origin of capacitance degradation depending on operation frequency, also called “frequency dependence” of the capacitance, was revealed. By performing dc and ac nonlinearity analyses, the effect of defects, especially oxygen vacancies, on the electrical properties of metal-insulator-metal (MIM) capacitors was investigated. Eventually, the mechanism of frequency dependence related to oxygen vacancy in the insulator of the MIM capacitor was identified.

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf x Zr1- x O2/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and Hf x Zr1- x O2 materials ( ${x} =0.75$ , 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization ( ${P}_{\text {s}}{)}$ of the Hf x Zr1- x O2 decreases from $25.9~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.5Zr0.5O2) to $20.3~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when ${P}_{\text {s}}$ further decreases to $8.1~ \boldsymbol {\mu }\text{C}$ /cm2 (Hf0.75Zr0.25O2), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of ${P}_{\text {s}}$ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.

This article investigates the applicability of dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET) as a biosensing element with the ability to assess the health parameters and disease onset. For this, employment of gate work-function engineering along with the gate-oxide-stack approach and asymmetrical doping at ${p}^{+}$ source and ${n}^{+}$ drain region are introduced for the first time to implement DMGOSDG-TFET-based biosensor. Also, a nanogap cavity is created by etching a portion of gate dielectric material toward the source end for the accomplishment of biomolecules conjugation in the proposed device. The main focus of this article is to estimate the underlying device sensitivity in the presence of different charged as well as neutral biomolecules. To explore such effects, different dielectric constants and negative charge densities of the biomolecules are considered independently in the nanogap cavity. Next, the sensing performance of the presented device is analyzed in terms of switching-ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), transconductance-to-current ratio ( ${g}_{m}/{I}_{ds}$ ), and average subthreshold-swing. A deep investigation of device performance is also performed with different fillings of the nanogap cavity and step-profiles arising out from the steric hindrance. The device sensitivity is analyzed for different cavity lengths and cavity thicknesses for the best outcomes. In addition, a comparative sensitivity analysis of DMGOSDG-TFET with single-material gate-oxide-stack double-gate tunnel field effect transistor (SMGOSDG-TFET) and metal–oxide–semiconductor field effect transistor (MOSFET)-based biosensor is also presented in this work. The device implementation and all the simulations are carried out using technology computer-aided design (TCAD) tool. All of the sensitivity-assessments disclose that DMGOSDG-TFET can be a good candidate for biosensing applications.

Conventionally, silver (Ag) electrodes for organic thin-film transistors (OTFTs) are prepared by evaporated method at high temperature. In this work, we report a new methodology to fabricate the Ag source/drain electrodes of flexible OTFTs arrays by chemically plated technique on polyimide substrate at room temperature. The indacenodithiophene-co-benzothiadiazole (IDT-BT) OTFTs with chemically plated electrodes obtain the saturation mobility of 0.25 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ . Furthermore, compared with high-temperature thermal evaporation method, the subthreshold swing of the IDT-BT OTFTs decreases from 1.97 to 0.89 V/dec with chemically plated Ag source/drain electrodes. The smaller threshold voltage and contact resistance are also obtained, owing to the change of work function. The bending tests indicate that the electrical properties of the devices maintain unchanged during tensile bending at a radius up to 1.4 mm. Moreover, the electrical property of the devices remains stable at a tensile bending cycle of 1000 cycles at a radius of 2.5 mm. This proposed methodology has great potential for flexible and wearable electronic devices.

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap’s position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs.

A major challenge for glass X-ray tube makers is the reduction in the tube size for portable or handheld applications. Size reduction is difficult mainly due to contact size restrictions for glass-to-metal welding. In high-voltage (60–70 kV) portable applications such as dental imaging, a distance of at least 5 mm should be maintained between the anode and the glass envelope to prevent the latter from burnout, which further limits reduction in the tube’s diameter. In this study, reduction in the size of a dental X-ray tube by approximately 43% is achieved by replacing the glass envelope with ceramic. Instead of welding, the ceramic body permits the use of brazing, which supports extremely small contact sizes. Additionally, due to the higher dielectric constant of ceramic, even less than 1 mm spacing is permissible between the envelope and the anode, enabling further size reduction. Despite the 43% reduction in size, limiting spatial resolutions of approximately 8 and 7 lines per mm are obtained for the ceramic and glass sealed tubes, respectively. Moreover, the two tubes obtain similar X-ray images of human teeth, verifying the potential of the compact-size ceramic X-ray tube in dental imaging.

In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage ( ${V} _{\text {BD}}$ ) was significantly enhanced, and the ${V} _{\text {BD}}$ of over 60 V is achieved in the TFT with the stair length ( ${L} _{\text {stair}}$ ) of $3~\mu \text{m}$ . The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs’ ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the ${V} _{\text {BD}}$ of the device. Finally, the exponential trade-off relationship between the ${V} _{\text {BD}}$ and the ON-state resistance ( ${R} _{\text{ON}}$ ) was established.

In this article, the preparation of HfLaOx gate dielectric thin films by the spin coating method is proposed. The in-depth physical properties of the as-prepared HfLaOx films were investigated as functions of annealing temperatures. Decided by the key performance indicators of current density, smooth surface, and areal capacitance of HfLaOx films with different annealing temperatures, optimized performance parameters with annealing temperature 550 °C have been obtained. To verify the feasibility of HfLaOx films as dielectric material, In2O3/HfLaOx thin-film transistors (TFTs) have been fabricated and device characterizations have been carried out. As a result, it has been detected that the In2O3/HfLaOx TFTs with optimized annealing temperature of 300 °C demonstrate superior electrical performance, including a high ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of ~106, a high $\mu _{\text {FE}}$ of 17.09 cm2V−1s−1, a low ${V}_{\text {TH}}$ of 0.09 V, a small interfacial trap states ( ${D}_{\text {it}}$ ) of $1.94\times 10^{{12}}$ cm−2, and a small threshold voltage shift of 0.23 V under PBS test and 0.11 V under NBS test after 3600 s bias stress, respectively. To confirm TFTs’ potential applications in logic circuits, a resistor-loaded inverter was integrated and the maximum voltage gain of 7.60 was demonstrated at an ultra-low operating voltage of 2.5 V. Current observations have indicated the great application prospects of solution-derived HfLaOx-gated TFTs in low-cost and excellent performance electronic devices.

A broadband dielectric window with high power handling capability for gyrotron traveling wave tubes (gyro-TWTs) had been designed based on the step-type impedance transition structure. The manufactured beryllium oxide (BeO) window can achieve a relative bandwidth of 35.3% with a maximum reflection of −20 dB in the ${X}$ -band, and the corresponding transmission loss is over −0.1 dB. The resonant spikes caused by engineering factors, including assembly tilt and gap, are investigated and analyzed. Thermal analysis shows that the BeO window can achieve a high average/CW power handling capability of over 232 kW within a wide frequency range. The fabricated input window has been successfully applied in our ${X}$ -band broadband and high-power gyro-TWT.

This article presents a novel lateral double-diffused metal oxide semiconductor (LDMOS) with integrated triple direction high- ${k}$ gate and field dielectrics (HKGF LDMOS). The main feature of the novel HKGF LDMOS is that the top silicon layer is etched to several pillars, and each pillar is surrounded by the high- ${k}$ dielectric from top and two sides. First, the triple direction high- ${k}$ dielectric surrounding the channel forms the high- ${k}$ metal gate structure together with the triple direction metal gate, which decreases the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},{\mathrm {sp}}}$ ) and threshold voltage ( ${V}_{TH}$ ) due to the increasing gate dielectric capacitance. Meanwhile, the triple direction gate structure broadens the channel width without enlarging device size, thus increasing the transconductance ( ${g}_{m}$ ) and further decreasing the ${R}_{ \mathrm{\scriptscriptstyle ON},{\mathrm {sp}}}$ . Second, the triple direction high- ${k}$ dielectric surrounding the drift region has strong modulation effect on the electric field and assistant depletion effect on the drift region, leading to the increasing of the breakdown voltage (BV) and decreasing of the ${R}_{ \mathrm{\scriptscriptstyle ON},{\mathrm {sp}}}$ . The simulation results indicate that when comparing with the conventional LDMOS, the proposed HKGF LDMOS not only decreases the ${V}_{TH}$ by 72.7% and ${R}_{ \mathrm{\scriptscriptstyle ON},{\mathrm {sp}}}$ by 48.1%, but also increases the ${g}_{m}$ and BV by 188.2% and 157.6%, respectively.

A simulation-based study of the variability of remnant polarization $({P}_{r})$ in a multigranular 3-D ultrathin ferroelectric (FE) capacitor is presented in this article. The Poisson-Voronoi tessellation (PVT) algorithm is used for the nucleation of grains in the FE region, which corresponds to the physical growth mechanism. The PVT algorithm implemented in MATLAB is coupled with TCAD simulations, to trace the FE hysteresis loop. The impact of both, area and thickness scaling on the variability of ${P}_{r}$ , is considered. It is found that amount of variability in ${P}_{r}$ increases as FE thickness decreases. In addition, FE with the smaller surface area exhibits a higher variability in ${P}_{r}$ compared to a larger surface area FE capacitor. Furthermore, the impact of dielectric content in the FE grains is analyzed. It is seen that the dielectric grains cause a very large amount of variability in the FE hysteresis loop. An increase in the dielectric grains also leads to a loss in the retentivity of the hysteresis loop.

Understanding the effective polarizability of dielectric and semiconducting interfaces has numerous applications in the development of sensors, computational elements, and energy storage devices. The complexity of the molecular and bonding topology makes it difficult to characterize the average polarizability that is needed for device modeling and optimization. Therefore, this article introduces a new technique to characterize and extract the volumetric average of the surface dipole polarizability. To accomplish this goal the aim of this research is to couple the experimental characterization of high density, in-plane capacitors with a finite element method (FEM) simulation model to investigate possible anomalous interfacial polarizability at abrupt dielectric interfaces. Specifically, the behavior at the interface between SiO2/air, Si3N4/air, and Al2O3/air are studied to identify the average surface permittivity values over a specified volume. Using electrical measurements from a high density in-plane interdigitated electrode (IDE) structure and quasi-electrostatic FEM simulation models, an average relative permittivity within a 1-nm interfacial region at 1 kHz is measured to be kSiO2/Air ~ 323, kSi3N4/Air ~ 58, and kAl2O3/Air ~ 160. In general, the new methodology presented in this article can be used to extract effective dielectric parameters that can be used to predict the electrical operation of devices that have a heterogeneous dielectric composition.

In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length ( ${L}_{\mathrm {ch}}$ ) and channel thickness ( ${T}_{\mathrm {ch}}$ ) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing.

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the corresponding possible mechanisms are discussed. These techniques have been successfully applied to the fabrication of NC-NMOSFETs with physical thickness 1.5-nm HfZrO, and underneath with 1.0-nm ZrO2 seed layer. The NC-NMOSFETs with much improved subthreshold swing (SS) of 38.6 mV/decade and nearly hysteresis free are developed with a gate length of 900 nm, and the SS is over 40 mV/decade smaller than that of the control-2 NMOSFETs with 2.5-nm HfO2 gate dielectric only.

Resistive random-access memory (RRAM) with atomic layer deposited (ALD) nitrogen-doped aluminum oxide (AlO x N y ) resistive dielectric appropriate for high-density 3-D vertical via array is demonstrated. With appropriate ALD electrodes, the RRAM exhibits almost forming-free, sub-microamperes programming currents, and appropriate resistance ranges. As the via size is scaled down, the set voltage and reset current decrease and the memory window widens, due to the 3-D nature of the device. Programming endurance of $5\times 10^{{4}}$ cycles and retention up to 10 years at 90 °C are demonstrated.

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- ${K}$ (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- ${K}$ (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( ${E}$ -field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the ${N}$ -buffer layer and ${P}$ -substrate, which increases the ${N}$ -buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk ${E}$ -field distribution is modulated by the ${E}$ -field peak generated at the position of varying ${K}$ dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical ${E}$ -field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {sp}}$ than the CTR LDMOS. Moreover, the figure of merit (BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {sp}}$ ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs.

Indium–gallium–zinc-oxide (IGZO) thin-film transistors (TFTs) gated with sputtered silicon dioxide dielectric were fabricated. Under different sputtering pressures of silicon dioxide, the device is able to produce transfer curves from clockwise hysteresis to anticlockwise hysteresis, corresponding to different operation modes and thus adding complementary performance by the same material system and device structure. In the interface trapping mode, the transistor exhibited inhibitory synaptic spiking behavior induced by positive stimuli. In the electric double-layer coupling mode, positive stimuli led to excitatory synaptic spiking behavior, while negative stimuli resulted in inhibitory synaptic spiking behavior. All the transistor and synaptic spiking behaviors are conducted within ±1 V range. Enriched functionality and ultralow operation voltage make sputtered SiO2-gated IGZO TFTs promising candidate for neuromorphic applications.

The effect of atomic-layer-deposition (ALD)-derived Al2O3 passivation layer on the interface quality of Er2O3/Al2O3/InP laminated stacks and the improvement of electrical performance has been investigated systematically. The chemical bonding states measured by high-resolution X-ray photoelectron spectroscopy (XPS) reveal that the ALD-derived Al2O3 passivation layer can effectively inhibit the diffusion of substrate elements to optimize the interface quality. Electrical characterizations show that the optimized sample has demonstrated improved electrical properties, including the large dielectric constant of 20 and the suppressed leakage current density of $4.10\times 10^{-7}$ cm2. In addition, the leakage current conduction mechanisms are also investigated as a function of thickness of Al2O3 passivation layer. The optimized interface state density extracted from the conductance method has reduced from $1.30 \times 10^{12}$ eV−1cm2 of Er2O3/InP to $7.27 \times 10^{11}$ eV−1cm2 of Er2O3/Al2O3/InP by adjusting the passivation layer thickness. As a result, it can be also confirmed that the passivation treatment is beneficial to inhibit the element’s diffusion and optimize the interface quality, significantly controlling the capacitor degradation caused by the leakage current through the stacked oxide layer.

We report the fabrication and characterization of atomic layer deposition (ALD)-titanium oxide (TiO2)/ silicon oxynitride (SiON)/n-Si gate-stack with ultrathin SiON (~4.46 nm) as an interfacial layer (IL) grown prior on the Si substrate followed by postdeposition annealing (PDA) of ALD-TiO2 in O2 ambient and N2 ambient. The structural characterization comprises the atomic force microscopy (AFM), the Fourier transform infrared spectroscopy (FTIR), the field emission scanning electron microscopy (FESEM), and the energy-dispersive X-ray spectroscopy (EDAX), whereas the electrical characterization includes capacitance–voltage ( ${C}$ – ${V}$ ), conductance–voltage ( ${G}$ ,– ${V}$ ), and current–voltage ( ${I}$ – ${V}$ ) measurements for the extraction of dielectric constant ( ${k}$ ), interface trap density ( ${D}_{it}$ ), effective oxide thickness (EOT), series resistance ( ${R}_{s}$ ), leakage current density (J), effective oxide charge ( ${Q}_{eff}$ ), barrier height ( $\Phi _{bo}$ ), ideality factor ( $\eta $ ), and breakdown voltage ( ${V}_{br}$ ). The determined values of ${k}$ , ${D}_{it}$ , EOT, ${R} _{s}$ , ${J}$ , ${Q}_{eff}, \Phi _{bo}$ , $\eta $ , and ${V}_{br}$ are 44, $6.3\times 10^{12}$ eV−1cm−2, 1.4 nm, 0.0623 $\text{K}\Omega $ , $2.5\times 10^{-10}$ A/cm2, $0.76\times 10 ^{15}$ cm−2, 0.423, 1.6, and −0.34, respectively. The pregrowth of SiON IL prior to TiO2 deposition has passivated the traps at the interface of SiON/TiO2, and the annealing of TiO2 film in N2 ambient has further worked over the existing challenges associated with scalability and gate leakage current.

Electrospinning one-dimensional (1-D) semiconductor nanofibers have been regarded as one of the most promising building blocks for future nanoelectronics with high performance because they can exhibit a broad range of device functions. However, electronic devices based on electrospinning-driven nanofibers often suffer from poor performance and inferior quality. In current works, continuous and uniform high-quality indium oxide (In2O3) nanofibers were obtained by electrospinning. The surface morphology, crystallinity, optical, and electrical properties of the In2O3 nanofibers were investigated by X-ray diffraction, scanning electron microscopy, optical spectroscopy, and electrical measurements. It has been detected that the field-effect transistors (FETs) with optimized electrospinning time of 30 s demonstrated superior electrical performance, including a high field-effect mobility ( $\mu _{{\mathrm {FE}}}$ ) of 9.1 cm $^{2}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ and a large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of 107. The high- ${k}$ Al2O3 dielectric layer has also been used to greatly reduce the operating voltage (from 30 to 3 V), significantly improve $\mu _{{\mathrm {FE}}}$ (to 27.7 cm $^{2}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ ), and strengthen stability over cycling. To prove the device’s potential in more complex logic circuit applications, a resistor-loaded inverter was further integrated, and the maximum voltage gain of 9.8 was demonstrated at an ultralow operating voltage of 3 V. The present findings have demonstrated that electrospinning can potentially be used as a straightforward and cost-effective means for the assembly of 1-D nanostructures for use in next-generation low-power devices.

We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in OFF-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements.

Binary oxides of Hf0.5Zr0.5O2 (HZO) have attracted considerable attention of the ferroelectric research community, owing to their excellent ferroelectric properties and CMOS compatibility. In particular, HZO films of a relatively high thickness (>10 nm) are studied widely for sensor and display applications. However, one of the major constraints of HZO materials is the formation of monoclinic phases (m-phase) with increasing film thickness resulting in the degradation of its remanent polarization ( ${P}_{r}$ ). Herein, we present a stress engineering method to achieve high ferroelectricity in thick hafnia using an interlayer. In our work, we attempted to address the aforesaid limitation of HZO by inserting a dielectric interlayer and elucidated the influence of interlayer on the relatively thick HZO films. high resolution TEM (HRTEM) analysis revealed that the presence of interlayer allows the growth of the top and bottom HZO layer in an independent direction thereby preventing the loss of ferroelectricity in HZO films with higher thickness by controlling its grain size. Similarly, grain angle incidence X-ray diffraction (GIXRD) and residual stress measurements suggest that the interlayer affects the o-phase formation from the t-phase owing to the tensile stress applied to the HZO films because of the coefficient of thermal expansion (CTE) mismatch between the HZO and interlayer. In our study, an improved $2{P}_{r}$ value of 30.2 $\mu \text{C}$ /cm2 was achieved by inserting a TiO2 dielectric interlayer in a relatively thicker HZO film. We believe that this approach can be adopted in various applications such as sensors, displays, and memory devices.

In this work, we present the substrate bias enhanced trap effects on time-dependent dielectric breakdown (TDDB) in GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) by experiment. Under different substrate biases, the shape parameter $\beta $ and scale factor $\eta $ of the Weibull distribution are extracted from the experimental data. A monotonical decrease in $\beta $ from intrinsic breakdown to extrinsic breakdown relating to the hole-emission from the acceptor-like buffer traps with increased negative substrate biases has been observed, while $\eta $ is increased at large positive substrate biases. This unexpected increase in $\eta $ suggests that the donor-like buffer traps play an important role with a longer lifetime. The trap mechanisms, relating to percolation path establishment, are analyzed based on progressive breakdown (PBD). The capacitance–voltage characteristics are measured during each stress cycle confirming the hole fluence and electron injection in the gate-stack layer with different trap distributions under various substrate biases. Finally, 2-D device simulations are carried out to probe for physical insight into the traps on TDDB failure mechanisms.

For extended interaction structure devices (EIDs), the determinants of field flatness are analyzed. It is found that the flatness of field distribution is determined by a cutoff condition existing in EIDs, which is based on the concepts of both resonant cavity and wave propagation. Such an analytical conclusion is verified by a novel scheme for the measurement of field distribution in an extended interaction oscillator (EIO) based on the perturbation technique. The sinusoidal-like axial field components with different flatness are obtained by utilizing the measured frequency shifts. Based on the cutoff condition, three field distribution patterns are established, including middle-concentrated, flat-distributed, and side-concentrated types. Particle-in-cell (PIC) simulations of a ${W}$ -band EIO show that three field distribution patterns have the advantages of low surface-loss power, high power-capacity, and low oscillating-threshold, respectively.

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

We fabricated Al2O3/LaAlO3/SiO2 (ALS) gate stacks on 4H-SiC, with LaAlO3 (LAO) film being annealed in O2 atmosphere. The ALS gate stack annealed at 700 °C exhibits a much higher breakdown effective electric field ( ${E}_{\text {eff}}$ ), which is approximately 1.8 times higher than that of traditional SiO2 gate oxide. The ALS gate stack also yields a low interface state density ( ${D}_{\text {it}}$ ) thanks to the intact LAO film. However, an annealing temperature as high as 800 °C induced traps in the LAO film and deteriorated the SiO2–SiC interface. The 700 °C-annealed LAO film with a high dielectric constant ( $\kappa $ ) of 14 and a low trap density, coupled with good electrical characteristics, makes it a promising gate dielectric for SiC power metal-oxide-semiconductor (MOS) device applications.

The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

A novel coplanar slow-wave structure (SWS) for application in millimeter-wave backward-wave oscillator (BWO) is proposed in this article. Unlike the traditional microstrip meander-line SWS with metal layers on both top and bottom surfaces of the substrate, the proposed SWS has a metal layer only on the top surface of the substrate. This significantly reduces the dielectric loading effect. The SWS is quite suitable for fabrication using PCB or microfabrication techniques and can be directly fed with coplanar waveguide (CPW), which has a lower loss than microstrip line. A design of the SWS presented here covers a −15-dB ${S}_{{11}}$ frequency range from 13.7 to 120 GHz. Simulation results for a BWO based on the proposed SWS show a tunable frequency range of 32.7 GHz and a maximum output power of 22.7 W at 114 GHz. To verify the proposed concept, a scaled version of the SWS is fabricated and measured S-parameters are presented. With a good potential for fabrication using microfabrication techniques, this structure can be a good candidate for millimeter-wave BWO applications.

To overcome the numerous challenges for the miniaturization of complementary metal–oxide–semiconductor (CMOS) technology, diverse materials have been examined using various characterization methods. Inelastic electron tunneling spectroscopy (IETS) has been regarded as a critical measurement technique to scrutinize materials. This is because the high sensitivity of IETS can provide important information regarding the material structures and molecular compositions (bonding structures, impurities, defects, and traps) in metal–oxide–semiconductor (MOS) structures, as well as the molecular conformation/isomerization, and contact geometry in molecular devices. This review introduces the background of IETS and recent applications of IETS on thin gate dielectrics, large DNA molecules, functional molecules, and diatomic molecules.

Due to the multipactor discharge breakdown, ferrite circulators have become the most susceptible component losing efficacy in high-power applications such as satellite payload systems. To date, effective suppression method of multipactor without affecting the electrical performance while keeping a high level of stability during in-orbit operation is still a technological challenge. In this article, a novel method based on the composite dielectric transformation is proposed for the considerable improvement of the multipactor breakdown threshold. The transformation medium is composed of dielectric rings of different permittivity, which could realize the uniform field transformation from the susceptibility region of multipactor to the dielectric/vacuum interface without acute change and discontinuity. In addition, the transformation medium is designed to guarantee little perturbance of the electrical performance and great convenience of fabrication and assembly. The experimental results of the ${S}$ -band circulator using this method demonstrated that while keeping very low insertion loss and isolation level, this method has improved more than 9 dB (≥850%) of multipactor threshold, showing very promising application potentials in antimultipactor designs for the spacecraft payload system.

In this article, the interfacial properties of nMOSFETs with different thickness high- $\kappa $ Al2O3 capping layer on an 8-nm SiO2 and TiN gate stacks have been investigated using electrical measurement and low-frequency noise at room temperature. It is shown that the predominant 1/ ${f}$ noise is governed by the number fluctuations mechanism. It is indicated that: 1) presence of an Al2O3 capping layer increases the noise power spectral density and, hence, the oxide trap density has an influence on the low-field mobility further and 2) effective work-function and the threshold voltage of nMOSFET should be modulated using the high- $\kappa $ Al2O3 capping layers.

We report the comparison of the atomic layer deposited polycrystalline (p-)/amorphous (a-) HfO2 bilayer gate dielectric with p-HfO2/a-Al2O3 for enhanced $\beta $ -Ga2O3 metal oxide semiconductor capacitors (MOSCAPs). A discrepancy in the temperature-dependent hysteretic behaviors is observed, and thus, pulse capacitance–voltage ( ${C}$ – ${V}$ ) measurements are employed to investigate interface properties at the border between the amorphous (Al2O3 or HfO2) and polycrystalline (HfO2) oxide layers. The proposed p-HfO2 /a-HfO2 exhibits similar interface trap densities ( ${D}_{\text {it}}$ ) at the interface between the bilayer dielectric and $\beta \text {-Ga}_{{2}}\text {O}_{{3}}$ , and shows lower border trap density ( ${N}_{\text {bt}}$ ). An effective barrier height of 1.62 eV for the p-HfO2 /a-HfO2 with a breakdown field of 9.1 MV/cm, which is higher than 1.01 eV of p-HfO2 /a-Al2O3, is obtained from the current density-voltage ( ${J}$ – ${V}$ ) characteristics using the Folwer–Nordheim model. Moreover, as compared with a p-HfO2 single layer, the additional a-HfO2 layer on top of p-HfO2 is beneficial to improve hysteretic and leakage characteristics, while maintaining its high-quality interface. The p-HfO2/a-HfO2 bilayer with improved interface properties as well as a large positive flat-band voltage of 4.7 V is a promising candidate for the metal/high- ${k}$ stack of $\beta $ -Ga2O3 MOSCAPs.

We demonstrate the electronic trap energy distribution ( $\Delta {E}_{IL}$ ) in the wide bandgap, nonconventional aluminum oxide phosphate (ALPO) dielectrics. The trap energy distribution has been measured by using the gate injection high-speed capacitance–voltage measurement technique and verified through conventional deep-level transient spectroscopy. The electronic trap energies in ALPO dielectrics were found to be influenced and, hence, tunable by the irradiation temperature. The nonirradiated dielectric film (NI-ALPO) displayed the maximum number of electronic traps at an energy level of 0.2 eV below the conduction band of silicon (Si-ECB). On the other hand, the dielectric film irradiated at 200 °C confirmed the highest number of traps at the location of 0 eV and at the same energy level of Si-ECB. In addition, the NI-ALPO dielectric contained over 90% of traps in the deep level of the bandgap (below Si-ECB). In contrast, the ALPO film irradiated at 200 °C accommodated a limited number of traps (~75%) at the deep level of the bandgap.

The ferroelectric (FE) polarization switching behavior in the HfZrO2 (HZO) FE/dielectric (FE/DE) stack is investigated systematically by charge responses from pulse measurements. The trapped charge density at the FE/DE interface related with the FE polarization switching is found to be $1.2\,\times \,10^{14}$ cm−2 according to the leakage-current-assist polarization switching mechanism. Furthermore, by the time-dependent nonswitching charge responses, the extra FE/DE interface trap density of $1.1\,\times \,10^{13}$ cm−2 is confirmed, which is not related but can be detected along with the FE polarization switching. The quantitative characterization reveals the huge amount of FE/DE interface traps and their dominant role in the FE operation of HZO FE/DE stack, which improves the proposed leakage-current-assist polarization switching model. This improved model provides a more comprehensive understanding of the polarization switching in the HZO FE/DE stack and new insights on HZO negative-capacitance (NC) and FE field-effect transistors (FETs).

Materials scientists have developed a wide variety of anisotropic insulators that could offer avenues to separately manipulate lateral and perpendicular electric fields if implemented as the gate insulators or spacers in field-effect transistors (FETs). However, there have been no works that have studied how the electrostatics of an FET can be engineered by using anisotropic insulators. We address this gap in knowledge by simulating metal–oxide–semiconductor FETs (MOSFETs) and tunnel FETs (TFETs) while separately varying the in-plane and out-of-plane permittivities of their insulators. Our results show that MOSFETs should have gate insulators and spacers with small in-plane and large out-of-plane permittivities to maximize their performance, and we demonstrate that an FET with a single anisotropic insulator that covers both the gate dielectric and spacers can outperform a similar structure that uses hafnium dioxide for the gate dielectric and air for the spacers. We also demonstrate that anisotropic gate insulators can greatly improve the subthreshold swing and ON-currents of TFETs, and we introduce a new type of heterogate dielectric for TFETs by manipulating the gate insulator’s in-plane permittivity. We anticipate that the results of this study will motivate experimental research toward developing FETs with anisotropic insulators.

Heterogeneous stacked electronics are one of the major topics in flexible electronics applications, which require high performances. At the same time, P(VDF-TrFE)-based polymers with unique characteristics, e.g., ferroelectric and flexible properties, also bring attention to heterogeneous stacked device applications. Since the interfacial characteristic has strong effects with performance and reliability, therefore, it becomes one of the key issues in P(VDF-TrFE)-based heterogeneous stacked devices. In this article, a mechanism of an interface trap charge-induced low-k interfacial layer was proposed and examined by experimental methods. To analyze the low-k interfacial layer effects, both general-doping (few 1015 cm−3) p-type and n-type silicon substrate were used. These experimental results showed that different types of silicon substrates have distinct interface properties. Then, different interface trap density ( $1.75\times 10^{12}$ – $4.1\times 10^{11}$ eV−1 cm−2) silicon substrates were fabricated to further analyze the low-k interfacial layer. These showed the substrate with the lowest interface trap density has less low-k interfacial effect than other substrates do. Based on these experimental verifications, the mechanism of interface trap charge-induced low-k interface characteristic was proposed. As a consequence, this interface trap–charge-induced behavior is a necessary consideration for applications of heterogeneous stacked devices.