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The hot-carrier lifetime evaluation method of a 90-V-level n-type lateral double-diffused MOS (LDMOS) is investigated in this brief. Our charge pumping experiments demonstrate that the on-resistance degradation of the device is induced by the combination effect of the hot-hole injection at field oxide region and the interface state generation at field oxide and accumulation regions. Thereby, the hot-carrier lifetime of the device was evaluated by the comprehensive model proposed by Moens, which considers the effects of both hot-hole injection and the interface state generation. However, our experiments found that multiple lifetimes were obtained based on the model proposed by Moens and some lifetimes have the risk of overestimation. To solve the problem, an improved hot-carrier lifetime evaluation method based on a novel semiempirical model is proposed. Further experiments and analyses illustrate that the proposed hot-carrier lifetime evaluation method can provide a definite lifetime that has no risk of overestimation for the investigated LDMOS and has improved the lifetime prediction precision compare to the method based on Hu’s model. [ABSTRACT FROM AUTHOR]

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years. [ABSTRACT FROM PUBLISHER]

A multifunctional vertical silicon-on-insulator-based metal-oxide–semiconductor (VSoI-MOS) field-effect transistor with trench body structure was designed. It can act as a high-performance transistor (HPT) or a capacitorless one-transistor dynamic random access memory (1T-DRAM), depending on the drain/source location and its electrical and transient performances. The VSoI-MOS operated in HPT mode exhibits favorable electrical performance with a lower drain-induced barrier lowering and subthreshold swing; the same device when operated in the 1T-DRAM mode exhibits a clear kink effect in its output characteristics, which facilitates the appearance of floating body effect and a significant improvement in the transient characteristics compared with HPT mode. This paper proposes a new erase mechanism for the 1T-DRAM mode. The mechanism is studied in detail by exploiting the self-heating of holes. [ABSTRACT FROM PUBLISHER]

The electron–hole (EH) bilayer tunneling field-effect transistor promises to eliminate heavy-doping band tails enabling a smaller subthreshold swing voltage. Nevertheless, the electrostatics of a thin structure must be optimized for gate efficiency. We analyze the tradeoff between gate efficiency versus ON-state conductance to find the optimal device design. Once the EH bilayer is optimized for a given ON-state conductance, Si, Ge, and InAs all have similar gate efficiency, around 40%–50%. Unlike Si and Ge, only the InAs case allows a manageable work function difference for EH bilayer transistor operation. [ABSTRACT FROM PUBLISHER]

Distributions of both electron traps and hole traps in metal/oxide/nitride/oxide/silicon (MONOS) structures were studied. These trap distributions were analyzed by using a combination of an avalanche-injection method and capacitance–voltage measurement. The thicknesses of the nitride layers in the MONOS capacitors were varied. It was found that electron traps are mainly located at both the top and bottom oxide/nitride interfaces, whereas hole traps are located at the interfaces as well as in the nitride bulk. This analysis clarified that electron-trap capability decreases anomalously in the range of nitride thickness of less than 4 nm. Moreover, the effective activation energy of electron emission also decreases at nitride thickness less than around 5 nm. These decreases are considered to be accounted for by detrapping due to the Coulomb repulsion between electrons at both interfaces and electron trapping in the interfacial transition layers. [ABSTRACT FROM PUBLISHER]

Degradation of polycrystalline silicon (poly-Si) thin-film transistor (TFT)-based CMOS inverters under AC operation is studied. Based on a previous drain current model of poly-Si TFTs including the kink effect, the voltage transfer characteristics of both fresh and stressed inverters are well described. It is determined that hot carrier of the n-TFT and negative bias temperature instability of the p-TFT are competing degradation mechanisms controlling the observed two-stage degradation of the inverter. Based on such mechanisms, degradation of inverter under various AC operation conditions can be qualitatively predicted. It is found that under given frequency and amplitude of the input pulse voltage, inverter's degradation can still be effectively suppressed by increasing the pulse falling time, and/or decreasing the low voltage duration. [ABSTRACT FROM AUTHOR]

We present a comprehensive study of hole transport in germanium layers on “virtual” substrates using a full band Monte Carlo simulation approach, considering alternate “virtual” substrate and channel orientations and including the impact of the corresponding biaxial strain, doping, and lattice temperature. The superior mobility in strained germanium channels with \langle\bar\1 \10\rangle orientation on a (110) “virtual” substrate is confirmed, and the factors leading to this enhancement are evaluated. The significant decrease in strain-and-orientation-induced mobility enhancement due to impurity scattering in doped material and at increasing lattice temperature is also demonstrated. Both factors determine how efficiently the mobility enhancement translates into transistor performance enhancement. Additionally, we shine light on the question of which factor has stronger impact in mediating the increase in mobility due to strain—the breaking of degeneracy for the heavy- and light-hole bands at the \Gamma point or the reduction in the density of states. [ABSTRACT FROM PUBLISHER]

We experimentally studied the high-field transport and mobility in nanoscaled \Si1 - x\Gex/silicon on insulator (SOI) PMOSFETs with gate length down to 17 nm. The study relies on the electrical characterization performed from room temperature down to 20 K. Strain relaxation in short channel has been evidenced by nanobeam electron diffraction, which explains the decrease of hole velocity and mobility with gate length. Despite this strain relaxation, a mobility gain is nevertheless preserved in sub-100-nm SiGe PMOS, with a maximum gain for 20% Ge in the layer. Short-channel mobility extraction reveals a lower contribution of Coulomb scattering for SiGe channel PMOS, which may explain this mobility improvement. We also demonstrate that the short-channel transport is governed by the Ge composition in the SiGe layer, with an optimum concentration of 20% Ge. We have finally evidenced a different temperature dependence of the limiting velocity at high field between SiGe and Si PMOS, suggesting that SiGe transport will be governed by inelastic scattering instead of ballisticity as L is shrunk. [ABSTRACT FROM AUTHOR]

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap-to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation. [ABSTRACT FROM PUBLISHER]

A novel array architecture is proposed for floatinggate nor-type nonvolatile memory cells. By embedding a floating \n+ region between two cells in each memory pair, punchthrough (PT) immunity is greatly improved. Since the operating cell and the cascade cell belong to two independent wordlines, bit-pattern effect on read and program characteristics is mitigated, and multilevel-cell storage can be easily realized. No additional program disturb has been found. Erase, endurance, and retention characteristics are comparable with its conventional counterpart. According to simulations, Lg as short as 56 nm, which is projected to serve for 28 nm technology node, is feasible without suffering a serious PT effect. [ABSTRACT FROM AUTHOR]

Self-consistently solving the Schrödinger and Poisson's equations in the six-band k \cdot p context can yield the valence-band structure in the inversion layers of pMOSFETs. In this numerically demanding process, the central processing unit (CPU) time is extraordinarily long. To overcome the hurdle, we construct a novel computational accelerator to intrinsically boost a self-consistent six-band k \cdot p simulation. This accelerator comprises a triangular-potential-based six-band k \cdot p simulator, a hole effective mass approximation (EMA) technique, and an electron analogy version of the self-consistent Schrödinger and Poisson's equations solver. The outcome of the accelerator furnishes the initial solution of the confining electrostatic potential and is likely close to the realistic one, which is valid for different temperatures, substrate doping concentrations, inversion hole densities, and surface orientations. The results on (001) and (110) substrates are supported by those published in the literature. The overall CPU time is reduced down to around 8% of that without the accelerator. This is the first successful demonstration of the EMA in the self-consistent hole subband structure calculation. The application of the proposed accelerator to more general situations is projected as well. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the operating principle and the injection efficiency of the punch-through-assisted hot hole injection mechanism for programming nonvolatile memory cells by means of full-band Monte Carlo transport simulations of realistic device structures. The effects of terminal bias and cell scaling on the injection efficiency and the uniformity of charge injection along the channel are analyzed in detail. [ABSTRACT FROM AUTHOR]

Hole mobility and velocity are extracted from scaled strained-Si0.45Ge0.55 channel p-MOSFETs on insulator. Devices have been fabricated with sub-100-nm gate lengths, demonstrating hole mobility and velocity enhancements in strained-Si0.45Ge0.55 channel devices relative to Si. The effective hole mobility is extracted utilizing the dR/dL method. A hole mobility enhancement is observed relative to Si hole universal mobility for shortchannel devices with gate lengths ranging from 65 to 150 nm. Hole velocities extracted using several different methods are compared. The hole velocity of strained-SiGe p-MOSFETs is enhanced over comparable Si control devices. The hole velocity enhancements extracted are on the order of 30%. Ballistic velocity simulations suggest that the addition of (110) uniaxial compressive strain to Si0.45Ge0.55 can result in a more substantial increase in velocity relative to relaxed Si. [ABSTRACT FROM AUTHOR]

A large drain current-gate voltage hysteresis of evaporated metal contact pseudo-MOSFETs (Ψ-MOSFET) is reported. The Ψ-MOSFET drain current exhibits a hysteresis when the gate voltage is swept from negative to positive and from positive to negative voltages. Optical illumination, elevated temperatures, and decreased sweep rate during the measurements eliminate this phenomenon. The reason for this behavior is related to electron-hole pair generation in the substrate. In this paper, we report systematic studies and device simulations to document and understand these substrate effects during Ψ-MOSFET measurements. [ABSTRACT FROM AUTHOR]

The spatial distribution of the electron-hole pairs generated by the electron beam is commonly called the generation volume or interaction volume. The generation volume affects the electron beam-induced current (EBIC) profile. This effect of the generation volume on the EBIC profile is particularly true for regions near to the semiconductor junctions. Mathematical models have been proposed for use in the computation of EBIC profiles. Three pear-shaped generation volume distributions were analyzed by comparing the resulting EBIC profiles to the profile obtained from the data using the Monte Carlo simulations. The result shows that the Bonard model gives an EBIC profile that is closest to the one computed using the Monte Carlo simulation. This result is easily observed in the first and the second derivatives of the semilogarithmic EBIC profiles. [ABSTRACT FROM AUTHOR]

In this brief, the effect of biaxial tensile strain on the hole mobility limited by substrate-impurity and interface-state Coulomb scatterings (μsub and μit, respectively) in an inversion layer of (100) / ‹110› pMOSFETs is investigated experimentally with strained-Si (s-Si) channels on relaxed Si1-xGex (x = 0.1-0.4) substrates. Our results show that biaxial tensile strain degrades the hole mobility limited by substrate-impurity Coulomb scattering (μsub), while it enhances the hole mobility limited by interface-state Coulomb scattering (μit) because of the increase in the average distance between holes and scattering centers at the Si/SiO2 interface after the tensile strain. These trends are opposite to that of electron ones. The different strain dependence between electrons and holes in terms of μsub and μit can be explained by a universal two-band model based on the subband structures of electrons and holes. [ABSTRACT FROM AUTHOR]

A comprehensive physics-based compact model for three-terminal undoped Schottky-barrier (SB) gate-all-around silicon-nanowire MOSFETs is formulated based on a quasi-2-D surface-potential solution and the Miller-Good tunneling model. The energy-band model has accounted for the screening of the gate field by the electrons or holes, which has been largely missed in the literature. Although SB-MOSFETs are essentially ambipolar devices, we show that the separate modeling of electron and hole currents is simple yet accurately predicts the final ambipolar current. Thinner oxide thickness is confirmed to be beneficial to SB-MOSFETs for both ON- and OFF-state currents. However, smaller nanowire radius (or thinner body thickness) is found to be only beneficial to SB-MOSFETs with high SB heights (SBHs) despite the OFF-state current being reduced significantly. For SB-MOSFETs with low SBHs, the tunneling-current-density enhancement due to a smaller radius is not able to compensate the reduction in the contact size, which leads to a degradation of the "ON" current. The drift current in the channel is shown to be negligible in SB-MOSFETs, and the tunneling/thermionic current through the SB represents the main current-limiting mechanism. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) cells are affected by structural relaxation (SR), which is the atomic-scale rearrangement of the amorphous phase of the chalcogenide material. Since SR affects the stability of electrical parameters of the PCM cell, such as resistance and threshold voltage, physics-based models for SR are necessary to analyze and predict the device reliability. This paper presents a physical model for SR in amorphous chalcogenide materials, linking the defect annihilation dynamics to the conduction behavior of the cell, hence to the electrical characteristics of the PCM cell. The model is able to predict the PCM cell characteristics as a function of annealing time, temperature, and read conditions. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) is a serious reliability concern for pMOS transistors. Although discovered more than 40 years ago, the phenomenon remains highly controversial in both experimental and theoretical terms. A considerable number of recent publications suggest that NBTI is caused by the following two independent mechanisms: 1) generation of defects close to the silicon/silicon dioxide interface and 2) hole trapping in the oxide. We have performed stress and recovery experiments at different temperatures and voltages that, quite surprisingly, reveal that all data can be scaled onto a single universal curve during stress, recovery, and restress. This suggests that in our samples, NBTI is caused by either a single dominant mechanism, which is more complicated than previously anticipated, or that the previously suggested mechanisms, i.e., hole trapping and defect creation, are actually tightly coupled. [ABSTRACT FROM AUTHOR]

We report on the degradation of MOS transistors under RE stress. Hot-carrier degradation, negative-bias temperature instability, and gate dielectric breakdown are investigated. The findings are compared to established voltage- and field-driven models. The experimental results indicate that the existing models are well applicable into the gigahertz range to describe the degradation of MOS transistors in an RF circuit. The probability of gate dielectric breakdown appears to reduce rapidly at such high stress frequencies, increasing the design margin for RF power circuits. [ABSTRACT FROM AUTHOR]

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si0.57Ge0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm. [ABSTRACT FROM AUTHOR]

In this paper, the transient analysis of an A1GaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor- type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities > 1e20 cm3 (> 5e12 cm2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states. [ABSTRACT FROM AUTHOR]

Program disturbs in NOR-type Flash arrays significantly degrade the tunnel oxide by hot-hole injection (HHI) induced by band-to-band tunneling at the drain overlap. This paper provides a comprehensive experimental and modeling analysis of HHI in Flash memories under program-disturb conditions. Carrier-separation measurements on arrays of Flash memories with contacted floating-gate (FG) allows for a direct investigation of hole-initiated impact ionization and HHI. A Monte Carlo (MC) model is used to simulate carrier multiplication and injection into the FG. After validating the MC model against experimental data for both secondary electron generation and HHI, the model is used to provide further insight into the hole-injection mechanism. [ABSTRACT FROM AUTHOR]

Experimental data and analysis show that overerase effects in NOR Flash memories increase with the electric field used during erasing. We found that the electric field is an accelerating factor for cell degradation during cycling. Tunnel oxide degradation reaches a critical level above which the cell starts showing erased threshold voltage instabilities possibly leading to single bit failure. Experimental data show that cell degradation during erasing has to be ascribed to hole injection rather than to electron injection and that both hole trapping and detrapping increase with the electric field. The total stress time required to reach the critical degradation level has been found to follow a 1/Eox exponential dependence which is similar to the oxide breakdown phenomena thus establishing a physical link between the two phenomena. Anode Hole Injection has been suggested as hole generation and injection mechanism occurring during erasing and it is shown to be consistent with the experimental data. [ABSTRACT FROM AUTHOR]

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified. [ABSTRACT FROM AUTHOR]

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated sub- threshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be ∼ 40 nm, located over the junction edge. [ABSTRACT FROM AUTHOR]

This paper investigates electron-hole generation in n-type MOS capacitors on 4H-SiC with the gate oxide directly grown in either 100% NO or 10% N[sub 2]O. High-temperature capacitance-transient measurements were used to determine and compare the contributions of carrier generation in the bulk and at the SiO[sub 2]-SiC interface. The effective generation rate in the bulk is similar in the MOS capacitors with either type of gate oxide, whereas the effective surface-generation rate is much lower in the case of oxides grown in 100% NO. Moreover, the effective surface-generation rate in these oxides is reduced to the level that is comparable to the effective bulk-generation rate. This result demonstrates the high quality of MOS capacitors with the gate oxide directly grown in 100% NO. [ABSTRACT FROM AUTHOR]

Presents an equivalent circuit model that describes transistors operating in pushout up to very high frequencies. Effect of the low mobility of holes on transistor operation; Use of commercial device simulation software tool to study the effect of a limiting hole velocity; Investigation of a conventional and a modified transistor.

Presents a study which developed a model of the hole direct tunneling gate current accounting for light and heavy hole's subbands in the quantized inversion layer. Characterization and parameter extraction; Description of the physical model; Calculation and discussion; Conclusion.

Provides information on a study which investigated the effects of mixed injection on the multiplication and noise characteristics of GaAs avalanche region and compared with the results for pure electron and hole injection. Growth and device fabrication; Measurements; Conclusion.

Investigates the generation characteristics of the neutral trap during various stress types using a proposed method for estimating the neutral trap density. Experimental preparation; Proposal of novel method for estimating neutral trap density; Measurement results of generated trap density and discussion; Conclusions.

Investigates a time-decay stress-induced leakage current (SILC) for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. Experimental preparation; Identification of SILC components; Proposal of trap model for each current components; Conclusions.