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This work investigates the effect of hole injection/light emission to suppress buffer-related dynamic ${R}_{\text {ON}}$ degradation in an E-mode GaN-on-Si active-passivation p-GaN gate high electron mobility transistor (AP-HEMT). The AP-HEMT features a thin p-GaN layer (i.e., the active passivation) covering the drain-side access region. The conventional p-GaN gate HEMT (Conv-HEMT) has been reported to mitigate the buffer trapping by hole injection/light emission from gate that pumps out the trapped electrons in buffer. In the AP-HEMT, hole injection and light emission occurs at the active passivation region as well. To evaluate the effectiveness of the hole/light pumping effect in AP-HEMT, back-gating measurements were performed to assess the recovery of buffer-related dynamic ${R}_{\text {ON}}$ . In the positive substrate voltage ( ${V}_{\text {SUB}}{)}$ sweep test, the ${I}_{\text {D}}$ of Conv-HEMTs drops significantly during the back-sweep due to the negative charges trapped in the buffer. However, the AP-HEMT shows no reduction in ${I}_{\text {D}}$ during VSUB back-sweeps. In the recovery test after a ${V}_{\text {SUB stress}}$ , the AP-HEMT experiences much smaller initial ${I}_{\text {D}}$ degradation and recovers much faster than the Conv-HEMT. These results confirm that the hole/light pumping effect in the AP-HEMT effectively suppresses buffer-related dynamic ${R}_{\text {ON}}$ degradation.

In this work, a high-voltage GaN-on-Si power integration platform is proposed, and a monolithically integrated half-bridge circuit is investigated by TCAD numerical simulations. The proposed platform exploits a local Si lateral etch from below the source contact of low-side transistor (LS-transistor). On a conventional GaN-on-Si platform, if the substrate is connected to the source of the LS-transistor, the high-side transistor (HS-transistor) suffers a negative back-gating effect that boosts up ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ; if the substrate is connected to the source of HS-transistor, the LS-transistor suffers significant buffer trapping owing to the positive back-gating effect. On the proposed platform, the substrate is connected to source contact of HS-transistor. The positive back-gating effect to the LS-transistor is effectively suppressed by the local Si lateral etch. With a lateral etch of $12~\mu \text{m}$ extending beyond the source contact of LS-transistor, the dynamic $\vert {V}_{ \mathrm{\scriptscriptstyle ON}}\vert $ of the device is reduced from 1.89 to 1.09 V, approaching that of a discrete GaN transistor with substrate-to-source connection (1.02 V). Therefore, the proposed platform provides an effective approach toward high-voltage GaN power integrated circuits.

In this study, a time-resolved extraction method is developed to investigate the threshold voltage ( ${V}_{\text {th}}{)}$ of a Schottky-type p-GaN gate high electron mobility transistor (HEMT) biased at high ${V}_{\text {DS}}$ . A testing platform is built which applies a triangular waveform to the gate of the transistor and extracts ${V}_{\text {th}}$ when the drain current equals 10 mA. ${V}_{\text {th}}$ of the device is biased at up to 370 V is presented. Being biased at a higher ${V}_{\text {DS}}$ , ${V}_{\text {th}}$ drops by more than 0.5 V for ${V}_{\text {DS}}$ beyond $\sim $ 50 V. The negative shift of ${V}_{\text {th}}$ at high ${V}_{\text {DS}}$ is a result of the elevated potential of the floating p-GaN layer, which is caused by the capacitive coupling between the drain and the p-GaN layer. As a comparison, the ohmic-type p-GaN gate HEMT and the Si superjunction MOSFET (SJ-MOSFET) exhibit negligible ${V}_{\text {th}}$ shifts. The negative ${V}_{\text {th}}$ shift partially recovers during the recorded time of 2000 s due to the leakage current through the gate/ p-GaN Schottky contact. A higher ambient temperature increases the leakage current, and the recovery is observed quicker. This work provides an effective approach to survey the time-resolved ${V}_{\text {th}}$ evolution of Schottky-type p-GaN gate HEMT biased at high ${V}_{\text {DS}}$ and serves as a guidance for the reliability design of GaN power transistors and switching circuits.