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Degradation and failure behaviors of the flexible low-temperature poly-Si (LTPS) thin film transistors (TFTs) under repetitive stretch stress parallel to channel length ( ${L}$ ) direction are investigated. A geometric effect is observed in degradation of the threshold voltage ( $\Delta {V}_{\text {TH}}$ ), which depends on the channel width ( ${W}$ ) and active area ( $\textit {WL}$ ), while has a weak correlation with ${L}$ . Three failure modes of TFTs are identified from their ${I}$ – ${V}$ characteristics: damage in the gate insulator (GI), channel traps generation, and metal line cracks. Failure statistics show that the GI failure has a low failure rate and follows the exponential distribution, while the other two modes have high failure rates in the early stage of the stretch cycles, and their failure distributions follow the limited failure population (LFP) model.

The degradation mechanism of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under pulse drain bias stress is investigated. Although the degradation mechanism is found to be a dc one, the shift of the transfer curve under the pulse drain bias (0–20 V) is unexpectedly larger than that under dc drain bias (20 V) within the same equivalent stress time. The degradation mechanism is proposed to be tunneling and trapping of electrons in the etching stop layer during the pulse peak time and that in the gate dielectric during the pulse base time under the extended drain electrode region of the a-IGZO TFT, where the occurrence of the latter is triggered by the former. A solution for enhancing the stability of the a-IGZO TFT is also suggested.

Roles of gate voltage ( ${V}_{G}$ ) and stress power in self-heating (SH) degradation of amorphous InGaZnO thin-film transistors have been clarified. Normally observed positive threshold voltage ( ${V}_{th}$ ) shift is attributed to the electron trapping mechanism, which is enhanced by both the effective ${V}_{G}$ and stress power. The effective ${V}_{G}$ plays a dominant role in most cases, while stress power takes control only if it is high enough. Following the positive ${V}_{th}$ shift, a second-stage negative ${V}_{th}$ backshift is also observed and is attributed to the water-related positive charges generation mechanism. It is enhanced by both stress power and effective ${V}_{G}$ for which stress power is found to be the dominant factor.

Degradations of elevated-metal metal oxide (EMMO) thin-film transistors (TFTs) under positive bias stress (PBS) and positive bias illumination stress (PBIS) are systematically investigated and compared. An intrinsic correlation between PBS and PBIS degradation is demonstrated. Continuous negative threshold voltage ( ${V}_{\text {th}}$ ) shift is observed under both stresses, with similar time-dependent $V_{\text {th}}$ shift and recovery behavior. Characterization parameters for dependencies of ${V}_{\text {th}}$ shift on both stress ${V}_{G}$ and temperature are also very close for the two degradations. PBS and PBIS degradation of EMMO TFTs and their correlation can be consistently understood based on a unified model, which emphasizes stress-induced accumulation of doubly-ionized ${V}_{O}$ traps at the back-channel interface, and is verified with simulation.

Different from the conventional degradation phenomenon under positive bias stress (PBS), the shift of the transfer characteristic curve of polycrystalline silicon thin-film transistors (TFTs) to the negative gate bias direction after PBS is observed and reported. The PBS degradation is found to be recoverable and the recovery proceeds at a faster rate first and then continues at a much slower rate. The recovery can be further accelerated at a higher temperature or by applying a negative gate bias. After detailed data analysis, the degradation mechanism is proposed to be the generation of protons in the gate oxide and its accumulation at the channel/gate oxide interface. The proposed degradation model could explain both the degradation phenomena and the recovery behaviors of PBS degradation.

Characteristics of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) are highly dependent on the hydrogen (H) content within the device architecture, for example in the etch-stop layer (ESL) of the elevated-metal metal-oxide (EMMO) TFTs. The serious apparent “short-channel effect (SCE)” was caused by the H diffusion from source/drain (S/D) to channel. Such SCE deterioration can be suppressed by thermal dehydrogenation at a cost of long annealing time, especially for a transistor architecture with a-IGZO S/D covered with H-rich silicon nitride (SiN x :H) and further capped with metallic H-diffusion barrier. The dehydrogenation efficiency is found to be significantly enhanced by fluorinating the a-IGZO. By optimizing the device architecture and/or the fluorination process to enhance the dehydrogenation, the SCE can be efficiently eliminated with well-maintained performance even for ${2}~\mu \text{m}$ -long a-IGZO TFTs.

A physical-based analytical kink current model for polycrystalline -silicon (poly-Si) thin-film transistors (TFTs) has been proposed. Two important mechanisms for the kink current, namely carrier impact ionization and the parasitic bipolar junction transistor effect, are physically included in the model without introducing any artificial parameters. The proposed kink current model is fully compatible with existing ON-state drain current models of poly-Si TFTs. Model parameter extraction procedure is presented, which is based on a group of output characteristics of poly-Si TFTs with different channel lengths. The model prediction straightforwardly calculated with a set of extracted parameters is verified by excellent agreement with experimental output characteristics measured from TFTs over a range of channel lengths and gate voltages.

Dynamic hot-carrier (HC) degradation can be effectively suppressed in four-terminal low-temperature poly-Si (LTPS) thin film transistors (TFTs) with a carrier injection terminal. In order to enhance the reliability of the four-terminal LTPS TFTs, geometry effect of the carrier injection terminal, such as width and location, on the dynamic HC degradation is systematically studied. It shows that a wider carrier injection terminal, which provides more carriers injection, can suppress the degradation more effectively. As for the location, if the injection terminal is adjacent to the edge of the drain depletion region, which extends into the channel at the falling time of the gate voltage pulses, the four-terminal TFTs can provide the best immunity to the dynamic HC degradation. The proposed optimization scheme can greatly enhance the reliability of LTPS TFTs, and the mechanism can be understood based on the nonequilibrium p-n junction degradation model.

An abnormal spontaneous degradation of polycrystalline Si thin-film transistors (TFTs) subject to dynamic bending stress is reported. Dynamic mechanical bending along either the channel-width or length direction causes degradation in flexible low-temperature polycrystalline Si TFTs, such as on-state current increase and threshold voltage positive shift. However, after the mechanical stress is removed, TFTs stored in a normal ambient continue to degrade spontaneously, with similar degradation behaviors. The amount of spontaneous degradation can be larger than the mechanical bending-induced degradation and is the most significant for a moderate number of bending cycles. The spontaneous degradation is a new challenge to TFT reliability under mechanical stress.

Mechanical reliability of flexible amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) is investigated by monitoring the electrical characteristic of TFTs before and after the dynamic stretch stress up to 300k cycles. With increasing the stretch cycles degradation features in a decrease in the on-state current, an increase in the off-state current, but almost no change in the subthreshold region or the threshold voltage. An approximately linear dependence between the on-state current degradation and the stretch force is observed, from which the critical fracture strain of a-IGZO thin film is determined to be 0.42%. It is proposed that a very few number of nanoscaled mechanical-stress-induced cracks, which originate from the interface between the channel and the gate insulator, and develop into both layers, but introduce only insignificant amount of interface defects, can fully explain the observed degradation.

Instability of a-InGaZnO thin-film transistors is experimentally investigated under synchronized ${V}_{g}$ and ${V}_{d}$ pulses’ stress. Degradation of the transfer characteristic in the forward measurement mode is much smaller than that in the reverse mode, if a typical drain bias of 5 V is applied. The degradation is found to depend on the equivalent dc stress time rather than the pulse transition edge. Larger pulse period and/or duty ratio of the voltage pulses cause more severe degradation. The degradation is affected by the recovery phenomenon, which occurs transiently when the pulsed stress is in the “OFF” phase, and enhanced by Joule heating-induced channel temperature rise. A degradation model is proposed, in which electrons’ trapping occurs at the channel/gate oxide interface, while extra electrons’ injection via thermal-assisted tunneling and interface defects’ generation occurs within a narrow region near the drain, forming a potential barrier therein. The model explains the observed degradation satisfactorily, and the result is verified by a 2-D simulation.

In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination.

In this paper, reduction of the gate-induced drain leakage (GIDL) current after drain bias sweeps for p-type polycrystalline-silicon thin-film transistor is reported, which is proposed to be due to local electron generation and trapping near the drain during the drain bias sweep in the kink current region. The reduction of the GIDL current during drain bias sweeps at successively lower gate biases undergoes a two-stage evolution behavior. The mechanism for the two-stage reduction behavior of the leakage current is clarified with the extraction and comparison of the activation energy for the leakage currents before and after the drain bias sweeps. Drain bias sweeps are also found effective in improving the uniformity of the leakage currents.

Self-heating degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under various stress powers. A two-stage degradation behavior with turnaround effect at the initial stage is characterized. The initial degradation stage is related to breaking of weak Si–H bonds. The floating-body effect by released hydrogen ions is responsible for the observed backshift of the transfer curve during the initial stress. On the other hand, the normal degradation stage occurs by breaking of strong Si–Si bonds and trap generation at grain boundaries (GBs) and the gate oxide/channel interface. Our model is supported by observed different activation energies related to two degradation stages and a direct observation of the continuous increase in GB trap density during the normal degradation. Furthermore, during the normal degradation stage, an anomalous continuous field-effect mobility increase along with its $V_{g}$ dependence shift is first observed. It is clarified that this behavior is not a true channel mobility increase, but a consequence of stress-related trap generation.