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Your search keyword '"Mitard, J."' showing total 9 results
Start Over Author "Mitard, J." Journal ieee transactions on electron devices
9 results on '"Mitard, J."'

1. Electrical TCAD simulations of a germanium pMOSFET technology

Author

Hellings, G., Eneman, G., Krom, R., De Jaeger, B., Mitard, J., De Keersgieter, A., Hoffmann, T., Meuris, M., and De Meyer, K.

Subjects
Germanium -- Electric properties, Metal oxide semiconductor field effect transistors -- Innovations, Simulation methods -- Usage, Computer-aided design -- Usage, Mathematical optimization -- Usage, Business, Electronics, Electronics and electrical industries
Published
2010

2. Quantification of drain extension leakage in a scaled bulk germanium PMOS technology

Author

Eneman, G., De Jaeger, B., Simoen, E., Brunco, D. P., Hellings, G., Mitard, J., De Meyer, K., Meuris, M., and Heyns, M. M.

Subjects
Complementary metal oxide semiconductors -- Analysis, Voltage -- Measurement, Germanium -- Electric properties, Electric currents, Vagrant -- Measurement, Business, Electronics, Electronics and electrical industries
Published
2009

3. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

Author

Arimura, H., primary, Dekkers, H., additional, Ragnarsson, L.-A., additional, Mitard, J., additional, De Heyn, V., additional, Mocuta, D., additional, Collaert, N., additional, Horiguchi, N., additional, Cott, D., additional, Boccardi, G., additional, Loo, R., additional, Wostyn, K., additional, Witters, L., additional, Conard, T., additional, Suhard, S., additional, and van Dorp, D., additional

Published
2019
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4. First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Author

Capogreco, E., primary, Witters, L., additional, Arimura, H., additional, Sebaai, F., additional, Porret, C., additional, Hikavyy, A., additional, Loo, R., additional, Milenin, A. P., additional, Eneman, G., additional, Favia, P., additional, Bender, H., additional, Wostyn, K., additional, Dentoni Litta, E., additional, Schulze, A., additional, Vrancken, C., additional, Opdebeeck, A., additional, Mitard, J., additional, Langer, R., additional, Holsteyns, F., additional, Waldron, N., additional, Barla, K., additional, De Heyn, V., additional, Mocuta, D., additional, and Collaert, N., additional

Published
2018
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5. Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Author

Witters, L., primary, Arimura, H., additional, Sebaai, F., additional, Hikavyy, A., additional, Milenin, A. P., additional, Loo, R., additional, De Keersgieter, A., additional, Eneman, G., additional, Schram, T., additional, Wostyn, K., additional, Devriendt, K., additional, Schulze, A., additional, Lieten, R., additional, Bilodeau, S., additional, Cooper, E., additional, Storck, P., additional, Chiu, E., additional, Vrancken, C., additional, Favia, P., additional, Vancoille, E., additional, Mitard, J., additional, Langer, R., additional, Opdebeeck, A., additional, Holsteyns, F., additional, Waldron, N., additional, Barla, K., additional, De Heyn, V., additional, Mocuta, D., additional, and Collaert, N., additional

Published
2017
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8. Superior NBTI in High- $k$ SiGe Transistors?Part I: Experimental.

Author

Waltl, M., Rzepa, G., Grill, A., Goes, W., Franco, J., Kaczer, B., Witters, L., Mitard, J., Horiguchi, N., and Grasser, T.

Subjects
TRANSISTOR design & construction, TEMPERATURE control of electronics, METAL oxide semiconductor field-effect transistors, SILICON industry, PERFORMANCE of transistors, EQUIPMENT & supplies
Abstract

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

Published
2017
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