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As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]