Search

We demonstrate tunnel FET (TFET)-based ternary CMOS (T-CMOS) which can operate at supply voltage ( ${V}_{DD}) V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current ( ${I}_{D}$ )–gate voltage ( ${V}_{G}$ ) characteristics have sub-60 mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state ( ${V}_{3rd}$ ) in the TFET T-CMOS, ${I}_{D}$ – ${V}_{G}\text{s}$ are analyzed with respect to various drain voltages ( ${V}_{D}$ ). As a result, it is revealed that ${I}_{D}$ – ${V}_{G}\text{s}$ of the n/p TFETs can have the wider flat ON-current regions at smaller ${V}_{D}$ by drain-side channel inversion and stable ${V}_{3rd}$ can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the ${I}_{D}$ difference between the n/p TFETs.

This article proposes a novel structure for tunneling-based ternary-complementary metal-oxide-semi conductor (T-CMOS) to break through the power scaling constraints of conventional binary-CMOS. The previous T-CMOS uses off-leakage band-to-band tunneling (BTBT) currents generated at the deep drain-to-substrate junction for the third voltage state, which allows ternary inverter configuration with only two single transistors. However, the high-dose ion implantation for the BTBT layer must affect the channel doping concentration, leading to the threshold voltage fluctuation. To avoid the interference of the BTBT layer dopants to the channel as well as to maximize the electrostatic gate controllability, vertically stacked gate-all-around (GAA) field-effect transistor (GAAFET)-type T-CMOS device is proposed. By simply changing the ground plane (GP) doping concentration in existing GAAFET fabrication, the BTBT layer can be formed completely apart from the suspended channel layers. The changes of the transfer characteristics and the transient output voltage characteristics depending on the key parameters such as the GP doping concentration and the gate work function are thoroughly analyzed for the proposed GAA T-CMOS through mixed-mode TCAD device and circuit simulations. It is concluded that the two key parameters should be optimized, otherwise the margin for the third voltage state and the switching speed is seriously degraded.

In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.

Read disturbance is analyzed in vertically channel-stacked NAND flash memory, which has string select transistors (SSTs) to access each channel layer independently. Additional read disturbance is observed at the cells adjacent to the selected cell in the unselected channel layers as well as typical read disturbance caused by repetitive Fowler–Nordheim tunneling (F-N) stress. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanisms. It is found that bitline-side [common-source line-side] adjacent cell is disturbed by the hot carrier injection (HCI), which results from positively [negatively] boosted channel potential by the rising [falling] of the voltage ( ${V}_{\text {unsel}}$ ) applied to unselected cells, respectively. A novel read operation, in which the selected cells are maintained in turned on state during the ${V}_{\text {unsel}}$ rising/falling and then are restored to their own states, is proposed to suppress the occurrence of the HCIs. As a result, it is revealed that the HCI-induced read disturbances are successfully suppressed by the proposed method.