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A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

This paper presents an experimental comparison of the block-oxide (BO) source/drain-tied (SDT) (BOSDT) polycrystalline-silicon (poly-Si) thin-film transistor (poly-Si TFT) with additional poly-Si body (APSB) against the zero-BO (ZBO) SDT (ZBOSDT) poly-Si TFT with APSB. The APSB scheme is created when the isolation process takes place after annealing of the source/drain regions. The experimental results show the superior electrical characteristics of the BOSDT-APSB poly-Si TFT over the ZBOSDT-APSB poly-Si TFT. The BO scheme is indeed useful in reducing the source and drain charge sharing. Although the ZBOSDT-APSB poly-Si TFT exhibits worse electrical properties, the combination of a ZBO (a buried oxide layer only under the poly-Si body) with an APSB can still be used to keep diminishing the charge-sharing effect. Furthermore, both devices can increase the cooling capability through their source/drain-tied structure.

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gate's ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.

In this paper, the influence of block oxide width (WBO) variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) was demonstrated and characterized. By utilizing the block oxide (BO) enclosing the sidewall of the Si body, the charge sharing from the source/drain (S/D) regions for a bSPIFET can be significantly reduced. Essentially, because the BO is adopted for a bSPIFET, its ultrashort-channel characteristics are similar to an ultrathin-body silicon-on-insulator (UTBSOI), although it possesses a thicker S/D region than a UTBSOI. From the simulation tests, it was also found that although the wider BO can suppress the ultrashort-channel effects (USCEs), the drain ON-state current ION slightly decreases because certain areas of the S/D are occupied by BO. Despite this problem, the bSPIFET still exhibits a good USCE control and a high-drive current. In addition, the self-heating effects are also ameliorated as a result of the natural body-tied scheme.