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The effects of [Al.sub.2][O.sub.3] dielectric capping and nitridation on physical properties, device performance, scalability, and reliability are examined. Findings reveal that [Al.sub.2] caps are beneficial to the pFET applications.

The impact of chlorine residue concentration in thin Hf[O.sub.2] films on the MOSFET device time-dependent dielectric breakdown (TDDB) is discussed. The results have shown that the presence of chlorine residue has no important impact on the trap generation and reliability of atomic layer deposition (ALD) Hf[O.sub.2] layers.

A study was conducted to examine the effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities for Si[O.sub.2]/Hf[O.sub.2]/TaN stacks. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-[kappa] bulk, as detected by both pulsed current-voltage and charge-pumping measurements.

An effective technique and methodology for the estimation of fixed charge components in high-kappa stacks was demonstrated by varying both the SiO[sub 2] and high-kappa dielectric thicknesses. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were grown on wafers to estimate the entire interfacial and bulk charge components. This method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers.

The characteristics of a bi-layer gate stack, consisting of an Hf[O.sub.2] layer and a Si[O.sub.2]-like interfacial layer, fabricated by a remote plasma oxidation (RPO) process, and the impact of the gate stack on transistor performance and reliability are described. The Si[O.sub.2]-like interface improves the mobility with reduced interface states and full oxidation and the controlled Si[O.sub.2]-like interface have shown RPO as a promising way for gate-stack optimization.

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the "one-composition-at-a-time" approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Φm) extraction for Ta1-xAlxNy alloys as metal gates on HfO2, for complementary metal-oxide-semiconductor applications, by automated measurement of over 2000 capacitor devices. Scanning X-ray microdiffraction indicates that a solid solution exists for the Ta1-xAlxNy libraries for 0.05 ≤ x ≤ 0.50. The equivalent oxide thickness maps offer a snapshot of gate stack thermal stability, which show that Ta1-xAlxNy alloys are stable up to 950 °C. The Φm of the Ta1-xAlxNy libraries can be tuned as a function of gate metal composition over a wide (0.05 ≤ x ≤ 0.50) composition range, as well as by annealing. We suggest that Ta0.9Al0.1N1.24 gate metal electrodes may be useful for p-channel metal-oxide-semiconductor applications. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al2O3 layer between the high-K dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiOx capped with 9 Å of Al2O3 obtains a low long-channel Vt of —0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm2 ⁄V · s at 0.8 MV/cm (92% of universal value), a negligible equivalent. oxide-thickness (EOT) increase of 0.1 Å (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of —0.7 V. This indicates that Al2O3 caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al2O3-capped HfSiOx is not favorable because it increases the Vt by 50—140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5—0.8 Å and the Vt instability by 5–13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, posthigh-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO2 interface. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, we reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, we conclude that the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2. [ABSTRACT FROM AUTHOR]

The effects of source/drain activation thermal bud- get and premetallization degas conditions on interfacial re- growth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-κ bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 °C spike for t = 1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 °C for t = 60 s). For 1000 °C spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing. [ABSTRACT FROM AUTHOR]

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Å, a leakage current of 1.5 A/cm² at VG = 1 V, a peak mobility of 190 cm²/V · s, and a drive-current of 815 μA/μm at an OFF-state current of 0.1 μA/μm for VDD = 1.2 V. Identical gate stacks processed with a 1000-°C spike anneal have a higher peak mobility at 275 cm²/V · s, but a 5-Å higher EOT and a reduced drive current at 610 μA/μm. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 °C) for a ten-year lifetime, whereas positive-bias temperature-instability :measurements indicate a sufficient lifetime for operating voltages below 0.75 V. [ABSTRACT FROM AUTHOR]

Bi-Iayer gate stacks consisting of a HfO2 and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400 °C due to radical oxygens, leading to an improvement in the quality of HfO2 with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO2 -like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO2-like interface demonstrate RPO as a promising way for gate-stack optimization. [ABSTRACT FROM AUTHOR]

Dielectric relaxation currents in SiO2 /Al2O3 and SiO2 /HfO2 high-κ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-κ dielectric stacks. It is found that high-κ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-κ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO2/high-κ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO2/high-κ interface is a key requirement for high-κ dielectric stack application and reliability in MOS devices. [ABSTRACT FROM AUTHOR]