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This paper presents a new and simple finite-control set model predictive control strategy to reduce the torque ripple in permanent-magnet synchronous machines (PMSMs). The method is based on minimizing a cost function that considers the flux linkage torque harmonics obtained from a discrete-time model of the machine. The power converter switching state that minimizes this cost function is selected and applied during a whole sampling period. Additionally, it is proposed to mitigate the other source of torque ripple, known as cogging-torque, using a feed-forward signal applied to the torque control loop. A hybrid method that uses the output information from an observer and look-up table is presented to obtain a good cogging-torque estimation and thus an accurate mitigation of this disturbance torque at low rotational speed. Experimental results demonstrate the good performance of the torque ripple compensation methods presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

For interleaved boost-type converters, both functions of voltage regulation and current balance are important. In this paper, the decoupled current-balancing control (DCBC) with two parallel loops is proposed. At first, the small-signal transfer functions of the voltage-regulation loop and the current balancing loop to the controller output are derived. The results show that the voltage-regulation loop and the proposed current-balancing loop are nominally decoupled. That is, two PI-type controllers can be designed independently and included to implement the proposed DCBC. Additionally, the single-sensor sampling-current strategy is proposed to obtain two average inductor currents by sensing only the sum of diode currents. All the controllers are implemented in field-programmable gate array (FPGA). The provided simulation and experimental results demonstrate the proposed DCBC. [ABSTRACT FROM PUBLISHER]

This paper deals with embedded real-time (RT) simulators applied in power electronic applications and implemented in low-cost field-programmable gate arrays. Indeed, such simulators' intellectual properties (IPs) are not only intended for hardware-in-the-loop (HIL) testing but also can be advantageously embedded within digital controllers to ensure functions such as observation, estimation, diagnostic, or health monitoring. Conversely, to the HIL case, the main challenge when designing such simulators' IPs is to cope with their complexity having in mind that, in the case of embedded systems, the available hardware resources are limited due to the cost. Furthermore, this challenge is strengthened by the need of very short simulation time steps that is typically the case when simulating power converters. By this way, this paper presents the design of an embedded RT simulator of a three-phase grid-connected voltage-source rectifier, based on the associated discrete circuit modeling approach. This IP is associated with the one of a three-phase $RL$ filter, and both are implemented within the rectifier controller to estimate the grid currents. The latter is injected in the controller when a fault is detected in the current sensors. The ability of this estimator to guarantee the service continuity in case of faults has been validated through HIL tests and experiments. [ABSTRACT FROM PUBLISHER]

Single-stage power-factor-corrected (S2PFC) power supplies usually suffer from high voltage stress, due to lack of control on the intermediate bus capacitor voltage. In the past, analysis of such voltage stress was mostly based on steady-state condition without providing sufficient explanation during the transient circuit operation. This paper revisits the problem at circuit level and reports that the root cause is due to the inherent negative current feedback property of the output inductor or the transformer operating in continuous conduction mode (CCM). Based on the finding, this paper further proposes a new approach to reducing the voltage stress by adding an auxiliary circuit branch to existing S2PFC converters. The additional circuit branch limits the effect of negative current feedback by suppressing the change of output current slope due to change of load. This assists the pulsewidth modulation controller to track the change of load better such that the bus capacitor voltage range is reduced through duty cycle control. The auxiliary circuit branch also reduces reverse-recovery-related losses of the converter under CCM operation. A laboratory prototype using the popular boost PFC converter combined flyback dc/dc converter was built and tested to confirm the analysis and effectiveness of the approach. [ABSTRACT FROM AUTHOR]

One of the main technical challenges associated with the modular multilevel converter (MMC) for any application is the optimal control of its states. Optimal control of the MMC requires determination of the following: 1) an accurate MMC model, 2) the MMC states to be controlled and their corresponding reference trajectories, and 3) an appropriate controller type/form and its parameters. The aforementioned tasks lead to the formulation of a multistate control optimization problem, which is tackled in this paper. This paper enhances the accuracy of the existing MMC state-space model by including the following: 1) a piecewise affine insulated-gate bipolar transistor/diode model and 2) the impact of dead time. This paper also proposes a simulation-based gradient-descent optimization algorithm (cosimulation) to optimize the controller gains, given the controller type/form and the reference state trajectory. The theoretical proofs of the gradients required in the optimization algorithm are also provided. The aforementioned optimization algorithm is applied to a variable-frequency MMC-based drive system. Experimental results on a scaled-down prototype and simulation results on a real-world application are provided to validate the accuracy of the proposed MMC model and to show the effectiveness of the proposed optimization algorithm. [ABSTRACT FROM AUTHOR]

This paper investigates time-domain analysis of sampling effect in digital pulsewidth modulation (DPWM) of dc–dc converters. The relation between the sampling delay, duty ratio, and multisampling factor (sampling to carrier frequency ratio) has been characterized. The sampling delay of the digital controller used for DPWM of the dc–dc converter has close relation with the actual pulsewidth-modulation output. An increase in the multisampling factor can reduce the delay effect of the DPWM. The output voltage varies as a stepped function of the duty ratio instead of the linear function as observed in ideal modulation. It is shown in this paper that this delay is a periodic function of the duty ratio. The effect of variations in the sampling frequency, switching frequency, and modulation index has been analyzed. The proposed sampling effect has been verified analytically for the buck, boost, and buck–boost dc–dc converters. The experimental results for the buck and boost converters have been obtained with the control circuit realized through a field-programmable gate array-based digital controller. [ABSTRACT FROM PUBLISHER]

This paper describes a systematic procedure using power flow graphs for generating all possible double-input single-output (DISO) dc/dc converters. To maximize the generality of applications, the input ports can possibly be connected with voltage source(s) or current source(s), and the output port can be connected with a voltage load or current load. The control methods are described in this paper. A DISO converter with two voltage sources and one voltage load is taken as an example to analyze a few key properties of practical relevance, including input voltage range, efficiency, power distribution, and switching stress. A popular application of DISO converters involves the use of a battery as storage element, and for this specific case, possible choices for the converters, the control method, and the attainable efficiency are discussed. Finally, experimental results are presented to verify the analytical results. [ABSTRACT FROM PUBLISHER]

Back-to-back converters have been typically used to interconnect microgrids. For a back-to-back current-source converter, the dc-link current ripple is one of the important parameters. A large ripple will cause electromagnetic interference, undesirable high-frequency losses, and system instability. Conventionally, with a given switching frequency and rated voltage, the current ripple can be reduced by increasing the dc-link inductor, but it leads to bulky size, high cost, and slow dynamic response. To solve this problem, this paper reveals that the current ripple can be significantly reduced by adjusting the gate patterns of space vector modulation between the rectifier and the inverter in a back-to-back converter. The experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

A merit of the interleaving reducing the switching harmonics allows for the reduction of the filter inductance. However, in the case of direct parallel voltage source inverters (VSIs), a severe circulating current occurs. To suppress the high frequency circulating current, coupled inductors (CIs) for the high impedance is inserted. However, the employed CIs induce a positive- or negative-sequence circulating current (i.e., a cross current) besides the zero-sequence circulating current already mentioned in the other papers. Due to different impedances developed by the current characteristics and the cross current in the CIs, VSIs becomes unstable when the resonant controllers are applied for the harmonic compensation such as 5, and 7th harmonics. In this paper, the cross currents and the impedances of CIs varying with the current characteristics are mathematically analyzed, and a novel current controller is proposed to solve this stability problem. The experimental results validate the proposed control scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a space-vector modulation (SVM) algorithm for a five-phase open-end winding motor drive system, fed by a dual nonsquare matrix converter (MC). The input to each of the MCs (MC-1 and MC-2) is a three-phase utility grid, and the output is a five-phase with variable voltage, variable frequency capability. The major contribution of this paper is the elimination of the detrimental common-mode voltage (CMV) that appears across the motor winding. In addition, the proposed SVM allows for a unity power factor at the input side, while boosting the output phase voltage by up to 150% of input. This paper presents a comprehensive analysis, to obtain the expression for the SVM modulating signals that are used to generate the switching pulses for the MC. To verify the idea, a modular, reconfigurable 5-kW MC prototype, feeding a five-phase induction motor is built. The control algorithm is implemented on a dSPACE-1006 platform. The test shows that the CMV is successfully eliminated from the motor winding. Other results (i.e., current and voltage waveforms) are also found to be in very close agreement with the theoretical prediction and MATLAB simulation. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel control method for an asymmetrical-cascaded-multilevel-converter-based hybrid energy storage system (HESS), which includes one battery and several electrical double-layer capacitors (EDLCs). Traditionally, it is challenging to control the power distribution between different cascaded H-bridges by using different energy storage components as dc sources. In this paper, a feedforward space-vector-modulation (FFSVM) technique is used to distribute the active power between the battery and EDLCs. With the proposed voltage feedforward mechanism, the HESS can flexibly operate in the normal operation mode, the high-power output mode, and the reverse power absorption mode. The principle and effectiveness of the improved FFSVM technique are analyzed. Meanwhile, the state-of-charge-balancing mechanisms are introduced. The simulation results obtained in MATLAB/Simulink as well as the experimental results of a hybrid energy storage test bed based on the proposed system are presented to verify its performance. [ABSTRACT FROM PUBLISHER]

This paper presents a uniform control strategy for the bidirectional ac/dc interlinking converter (BIC) in hierarchical controlled hybrid microgrid. The uniform control strategy unifies different control structures for multifunctional BIC in terms of power management, ac and dc voltage support. With the unified control structure, various triggering mechanisms for BIC mode-switch are not compulsory in response to the relevant scenario changes in the power network. Therefore, the negative consequences, such as unsmooth transition and system collapse due to the inaccurate or slower mode switch, can be avoided. Moreover, the uniform control strategy is also applicable for the hierarchical controlled hybrid microgrid, whose control architecture is typically comprised of the centralized and decentralized levels. This enables the communication fault ride-through capability and the impact from the communication failures can thus be mitigated. To sum up the above two features, the proposed control strategy is able to provide a smooth operation for the BIC without control mode switch in the event of unintentional scenario changes in power or communication network. To verify the validity of the proposed uniform control strategy, the controller hardware-in-the-loop experimental results have been provided in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents an improved saliency-based position sensorless drive of an interior permanent-magnet synchronous machine (IPMSM) with a single current sensor, used for low cost applications. The phase current, reconstructed from a dc-link current, shows a reconstruction error resulted from the difference of the sampling point from that of a full current sensor drive. This reconstruction error results in degradation of the overall sensorless control performance. In this paper, we analyze the impact of the reconstruction error depending on the injection frequency for a high frequency voltage signal injection sensorless control. Based on this analysis, we propose an improved position sensorless drive that employs a new current reconstruction method. In order to minimize the reconstruction error, the proposed current reconstruction method predicts the dq-axis currents with the same sampling point as a full current sensor drive. Several experimental results are provided to verify the analysis of the reconstruction error and the proposed method's improved sensorless control performances. [ABSTRACT FROM PUBLISHER]

This paper develops a novel voltage equalizer by combining wireless power transfer (WPT) and a voltage multiplier (VM) for series-connected energy storage cells. The physical isolation achieved by WPT can offer several unique benefits that traditional equalizers can hardly provide. In this paper, the characteristics of a multiple-output VM are analytically discussed and used to develop an equivalent one-output VM model. Based on this model, parameters of the WPT system are properly designed. The proposed design methodology can achieve a single-switch voltage equalizer without feedback control, which dramatically decreases the circuit complexity and cost. Moreover, this methodology can naturally ensure a robust system under small coil misalignment. In the experiment, the proposed system is built to balance four series-connected ultracapacitor modules. The system efficiency is 72.8% at a load power level of 10 W. [ABSTRACT FROM PUBLISHER]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

High-frequency components of acoustic noise radiated by the electric powertrain make the subjective perception of electric vehicles worse than expected under certain operating conditions. In order to investigate the influence of acoustic components on sound quality, a pulse width modulation (PWM)-fed electric powertrain is studied in this paper. First, the acoustic noise of the electric powertrain is collected in a semianechoic chamber. Then, two types of acoustic components of the electric powertrain, namely harmonic order noise and switching noise, are distinguished through the analyses of supplied current from the inverter and gear vibration. Furthermore, the relationship between subjective perception and spectral characteristics of the noise is discussed, based on which sensitivity is established. Subsequently, the contributions of acoustic components to psychoacoustical parameters are determined. After that, a sound quality model of the acoustic noise radiated by the electric powertrain is established. The comparison between jury test and prediction shows that the established model can be used for sound quality evaluation of the electric powertrain. Finally, the influences of harmonic order noise and switching noise on subjective perception are discussed. The main original contribution of this paper concerns the influences of harmonic order noise and switching noise radiated by PWM-fed electric powertrain on sound quality. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel fuzzified mechanical sensorless speed estimation technique for permanent magnet direct current (PMDC) brushed motor operated with pulse width modulation (PWM) based terminal voltage. For replacement of conventional mechanical speed sensors, few mechanical sensorless speed estimation techniques have been reported recently in the field of PMDC brushed motor. In this paper, a novel technique is applied over a recently reported semianalytical dynamic time-domain PMDC brushed motor model incorporating space-domain effects, namely slotting effect and commutation phenomenon to simulate the proposed estimation process. Ripple and back electromotive force based standalone estimation approaches are hybridized in order to eliminate uncertainties in all regions of estimation. In this paper, a discrete fuzzified hybrid speed estimation model has been proposed with adequate dynamic simulation responses. Further the proposed discrete speed estimation model has been applied experimentally over a PWM-driven 24-V, 12-teeth, 100-W PMDC brushed motor and various dynamic real-time responses have been compared with conventionally captured speed samples to validate the proposed model. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage. This stage is shared by all inverter output phases, thus increasing the number of output voltage levels while reducing the overall number of active devices compared to traditional topologies; therefore, it is called a reduced multilevel converter (RMC). The converter is not capable of reducing the blocking voltage of the devices; hence, unlike other multilevel converters aimed at medium-voltage applications, this converter is interesting for low-voltage- and high-power-quality-demanding applications such as photovoltaic inverters, wind energy conversion systems, and uninterruptible power supplies. The main novelty behind the proposed concept is the basic dc cell used to generate the variable dc-link voltage, which includes a controlled path through the floating capacitors to provide the necessary degree of control to enable a shared multilevel dc link for all the output phases of the converter. The dc cells are connected in a multicell structure to increase the number of levels of the converter. A five-level version of the RMC topology is briefly compared to other five-level converters such as the five-level active neutral-point-clamped converter and the five-level flying capacitor converter. This paper presents the structure of the new topology with its operating principle, switching states, main characteristics, and experimental validation using finite-control-set model-predictive control. [ABSTRACT FROM PUBLISHER]

In applications that demand single-input dual-output (SIDO) or dual-input single-output (DISO) dc–dc converters, employing two separate single-input single-output (SISO) converters is a solution. However, the number of components is doubled, resulting in high overall cost. In order to reduce costs, this paper proposes a novel topology synthesis methodology, with which a variety of SIDO and DISO dc–dc converters with reduced components can be derived. The principle of topology synthesis states that integrated SIDO and DISO dc–dc converters can be easily developed from conventional SISO converters by replacing a diode with a basic cell inclusive of additional input/output port. The principle is effective for many SISO dc–dc converters, and as an example, topology synthesis based on buck, boost, buck–boost, Cuk, sepic, and zeta SISO converters is performed in this paper. In order to achieve better understanding of the proposed converters, the integrated SIDO Cuk converter is specifically analyzed and experimentally verified. In comparison with the conventional scheme of two separate SISO Cuk converters, good cross regulation is retained while the number of diodes, inductors, and capacitors is reduced in the proposed SIDO Cuk converter. In addition, zero-voltage-switching operation of one switch is achieved, contributing to lower switching losses. Finally, a prototype circuit with 48-V input and 156 V/1 A, 24 V/4 A outputs is built to validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

In this paper, new half-bridge and full-bridge topologies for a switched-boost inverter are proposed. These topologies have a high boost factor in comparison with conventional types. In addition, the proposed topologies have continuous input current and can generate zero-voltage level in output. In this paper, the operation of the proposed inverters in different operating modes is analyzed. Then, the values of inductors and capacitors are designed. Moreover, the used switching pattern and its logical diagram are introduced. A comprehensive comparison between the proposed and conventional topologies in terms of the boost factor, the number of elements, and the efficiency shows the good features of the proposed inverters. Finally, to verify correct operation of the proposed topologies and derived equations, simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

The nine-switch converter is a multiport converter having two three-phase terminals and a dc-link, just like a 12-switch back-to-back (BTB) converter, but with 25% reduction of active switch count. However, the reduction from 12-switch to 9-switch may not always be an efficient choice considering losses in the switches. Only the load–source combination for the ac–ac common frequency mode and the source–source combination for the ac–dc different frequency (ac–dc DF) mode have been reported, so far, to yield relatively lower loss for the nine-switch converter. This paper shows that the nine-switch converter can have relatively lower loss even with a load–source combination, instead of only source–source combination in its ac–dc DF mode—when the upper terminal is connected to a dc load and the lower terminal is connected to an ac source. Mathematical proof is presented with derivation of the particular operating parameters for which the nine-switch converter will have comparatively lower losses. The analysis is validated with simulation and experimental results of a 1-kW system. Finally, the benchmark of the application criteria of the nine-switch converter for having lower conduction loss than the BTB converter is updated in this paper. [ABSTRACT FROM AUTHOR]

Digital current controllers have the key impact on the performance of grid-side converters and ac drives. The voltage disturbances are commonly suppressed by enhancing the controller with an inner active resistance feedback. In cases where the switching noise and parasitic oscillations introduce sampling errors, conventional sampling is replaced by the oversampling-based error-free feedback acquisition which derives the average of the measured currents over the past switching period. The time delay introduced into the feedback path creates difficulties in designing the current controller with the active resistance. In this paper, we introduce a novel structure of the current controller, which includes the error-free sampling and the active resistance feedback. Devised structure improves the disturbance rejection by extending the range of permissible values of the active resistance. Controller structure is based on the internal model principles, and it maintains the input step response unaffected. This paper comprises analytical design, the gain setting procedure, computer simulation, and experimental results obtained from an experimental setup with a three-phase inverter, digital controller, and a permanent-magnet synchronous motor. [ABSTRACT FROM PUBLISHER]

A novel hybrid pulse width modulation (PWM) technique is proposed in this paper for two parallel interleaved, two-level, three-phase voltage source inverters (VSIs). The two parallel interleaved VSIs are analyzed as a three-level (3L) inverter. A 3L inverter provides minimum line current ripple when nearest three voltage vectors are applied. In this paper, a novel carrier-based PWM technique is developed that ensures the application of nearest voltage vectors, keeping average circulating current to zero over a switching period. For carrier-based implementation of the proposed PWM, generalized common-mode (CM) offsets are derived in terms of maximum and minimum values of reference signals. Each 3L space-vector sector is divided into seven subsectors. For each subsector, a CM offset is calculated, addition of which to reference signals ensures the minimum line current ripple and zero average circulating current. Simulation and experimental results are provided to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

For power converters with inductive loads, a freewheeling path is needed for the current due to reactive power. The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Hence, an antiparallel SiC Schottky diode is normally implemented to eliminate its conduction. However, the external SiC Schottky diode is not fully utilized as it only works during the dead time. In this paper, the hard-switching SR is investigated in an SiC three-phase inverter and compared with a conventional inverter using freewheeling diode (FWD). An improved power loss model for the two inverters has been developed. It is found that the inverter using SR has higher efficiency due to the smaller switching loss. A 7-kW prototype of SiC three-phase inverter is built, which achieves a peak efficiency of 98.8% ($\pm$ 0.15%) and 98.5% ($\pm$ 0.15%) at 40 kHz using SR and FWD, respectively. This paper confirms that the SiC MOSFET is an ideal candidate for the SR. [ABSTRACT FROM PUBLISHER]

This paper investigates and evaluates the performance of a single-phase split-source inverter (SSI), where an alternative unidirectional dc–ac configuration is used. Such configuration is utilized in order to use two common-cathode diodes in a single device instead of using two separate diodes, resulting in minimum parasitic inductance in the commutation paths. In this paper, the analysis and modulation of the single-phase SSI using this alternative configuration is discussed, and the analysis of the low-frequency component in the dc side is introduced. Moreover, the features behind employing the triangular, the trailing-edge sawtooth, and the leading-edge sawtooth carriers with the single-phase SSI are discussed, and the differences among these carriers are highlighted. In order to highlight the performance of the proposed SSI, a comparative study is conducted with the two-stage architecture and the single-phase quasi-Z-source inverter (qZSI). The introduced analysis is enhanced with simulation results using MATLAB/PLECS models, where a 1-kVA single-phase SSI is designed and simulated. Finally, the designed 1-kVA single-phase SSI is implemented experimentally and tested at different operating points, i.e., at different voltage gains, and a maximum efficiency of $95.5\%$ is obtained. [ABSTRACT FROM PUBLISHER]

This paper proposes and validates model predictive control as an alternative control strategy for H-bridgeneutral-point-clamped (H-NPC) converters for single-phase grid-tied string photovoltaic (PV) systems. The presented control scheme achieves good quality current waveforms with unity power factor, dc-link voltage control, and neutral-point voltage minimization. Furthermore, the predictive controller has been further enhanced by including an average device switching frequency restriction and a $dv/dt$ mitigation. The main contribution of this paper is the avoidance of the potential leakage current due to parasitic capacitance of the PV modules by using a predictive model based control technique instead of modulated schemes and eliminating high-frequency common-mode voltage components. Experimental results during steady state and dynamic operation are presented to illustrate the behavior of the H-NPC converter commanded by the proposed control scheme. [ABSTRACT FROM AUTHOR]

The reduced chip size and unipolar current conduction mechanism make silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for high-frequency power electronics applications. Modeling the switching process of the SiC power MOSFET with parasitic components is important for achieving higher efficiency and power density system design. Therefore, this paper proposes a new concise yet accurate switching loss model for SiC power MOSFETs. Addressing the limitations in experimental measurements, numerical simulations are conducted to validate the proposed model taking the output capacitance Coss discharge and charge into consideration. The role of the parasitic components in the second-order model is discussed in depth for switching losses. Furthermore, this paper also provides guidelines in designing the gate driver for ultrafast SiC power MOSFETs. [ABSTRACT FROM PUBLISHER]

This paper proposes a wide-range zero-voltage-switching (ZVS) active-clamped current-fed push–pull converter for fuel cell application. The presented converter achieves ZVS for all of the primary switches and ZCS for secondary diodes from rated load to 10% full load over the wide input voltage variation, improving the overall efficiency. The ZVS of switches is realized by the energy stored in the transformer leakage inductance aided by the secondary parallel inductor. An additional active clamping circuit suppresses the voltage spike as well as assists in realizing ZVS of switches. Low-voltage-rated switches with low on-state resistance can be used. Moreover, the voltage-doubler rectifier is adopted to release the reverse-recovery problem of rectifier diodes and reduce turns ratio of the high-frequency transformer. Detailed steady-state operation, analysis, design, control, comparative study, and experimental results are discussed in depth in this paper. Finally, a 200-W prototype has been built in the laboratory to verify the effectiveness of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper proposes a family of soft-switching bidirectional converters. In many applications, the bidirectional converters operate over a wide range of duty cycle and load variations. In the proposed converters, in order to extend the zero-voltage switching operation range, two supplemental voltage sources utilizing passive components are implemented in the auxiliary circuit. By using this method, the soft-switching features are ensured for an extensive range of the converter duty cycles. This is achieved independent of the output power value or the converter operation mode, and so, soft switching is ensured within the entire converter operating region. In these converters, all semiconductors components are soft switched, and the auxiliary circuit does not contribute to the complexity of the control circuit. Also, no extra voltage stress exists on the main switches and the voltage stress on the auxiliary switches is lower than the main switches voltage stress. In this paper, the proposed bidirectional buck/boost converter is analyzed and to confirm the feasibility of the proposed method, experimental results of a 150-W prototype converter are presented. [ABSTRACT FROM PUBLISHER]

The selective harmonic current mitigation pulsewidth modulation (SHCM-PWM) technique can be used in cascaded multilevel converters to extend the harmonic reduction spectrum, reduce the coupling inductance and increase the efficiency. The offline SHCM-PWM technique has small number of switching transitions as its switching angles can only change once in a fundamental cycle and relatively long time delays because it uses FFT. As a result, its dynamic response has a lot to desire. As it will be proven in this paper, in four-quadrant power converters, to have a good transient dynamic response, both active and reactive power must be controlled at least two times in a fundamental cycle. In this paper, a hybrid modulation technique is introduced. The proposed technique uses SHCM-PWM under steady state and phase-shift PWM (PSPWM) under transient. In addition, in order to extend the modulation index range and ensure that SHCM-PWM can process four-quadrant active and reactive power, the constraints of the switching angles for the SHCM-PWM are modified. Simulations and experiments are conducted on a seven-level cascaded H-bridge converter to verify the proposed technique. [ABSTRACT FROM PUBLISHER]

For the purpose of improving the performances of T-type neutral point clamped (T-NPC) photovoltaic (PV) grid-connected inverter under large grid, a passivity-based decoupling control scheme is proposed in this paper. First, the Euler–Lagrange (EL) mathematical model of a T-NPC PV grid-connected inverter with an LC filter is built based on the power circuit and operating principles. Second, with this EL mathematical model and passivity of the inverter, the passivity-based controller is designed by the damping injecting method. Third, by adopting a proportional integral regulator to directly control direct current (dc) voltage, together with passivity-based indirect control, better performances of the dc voltage control can be further obtained. With the proposed passivity-based controller, the PV grid-connected inverter can achieve both dynamic current decoupling under the synchronous rotating dq coordinate and dc side voltage dynamic decoupling, which can improve the quality of the current connected into the power grid. The passivity-based PV grid-connected inverter is with strong robustness against parameters perturbations of resistors and attenuating the influence of delay in the inverter. Moreover, the passivity-based decoupling control scheme proposed in this paper for the T-NPC PV grid-connected inverter has a simple structure, and is easily debugged and realized in engineering. Experimental results under 10-kW prototype show that the proposed control scheme is effective. [ABSTRACT FROM PUBLISHER]

This paper proposes an interleaved buck converter (IBC) with continuous input current, extremely low output current ripple, low switching losses, and improved step-down conversion ratio. Unlike the conventional IBC, the proposed converter has a continuous input current, and its output current ripple is extremely low. The proposed converter has a lower voltage stress in comparison to the conventional IBC and can also provide a high step-down ratio, which makes it a proper choice for high-power applications where a nonisolated step-down converter with low output current ripple and continuous input current is required. Also, the proposed converter can provide current sharing between two interleaved modules without using additional current-sharing control method. All of these benefits are obtained without any additional stress on the circuit components. A prototype converter with 200-V input and 24-V–10-A output is implemented to verify the theoretical analysis. Operational principles and experimental results are presented in this paper. [ABSTRACT FROM PUBLISHER]

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 \mu\s . Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency. [ABSTRACT FROM PUBLISHER]

Multilevel converters have been well studied for high-voltage high-power renewable energy applications. Owing to the multibranch structure, these converters can be operated under fault conditions in case of a loss of a branch or voltage cell. In this regard, this paper proposes a new active fault-tolerant space vector pulsewidth modulation strategy for single-phase faults in three-phase multilevel converters. The proposed modulation strategy treats the multilevel converter as a two-level converter by introducing an offset vector. A generalized approach is proposed to search for the offset vector and to adjust the modulation of the converter online under different fault operation conditions. Several short- and open-circuit faults have been demonstrated on a seven-level hybrid input-switched converter to prove the effectiveness of the proposed fault-tolerant scheme. [ABSTRACT FROM PUBLISHER]

A high-voltage tapped-inductor buck converter utilizing a novel autonomous high-voltage valve is presented in this paper. Its application as auxiliary power supply for high-power cascaded-converter submodules is discussed, followed by a presentation of the most challenging problems in designing a low-power high-voltage step-down converter. The TI-buck converter topology is analyzed, which together with the novel autonomous high-voltage valve overcomes most of the problems. Analytical expressions describing the operation as well as circuit simulations are presented. Finally, an experimental evaluation of a 3-kV 70-W prototype converter utilizing the proposed autonomous high-voltage valve with series-connected super-junction MOSFETs is presented. [ABSTRACT FROM PUBLISHER]

Due to high functional variety, wide power rating range, and relatively low product volumes, electronic systems for industrial application are difficult to economically be integrated on a chip. This paper presents the smart power gate array (SPGA), a novel application-specific integrated circuit (ASIC) platform exactly aimed at enabling cost-efficient single-chip integration of industrial electronic systems. The SPGA combines a low-voltage mixed-signal gate array with a structured high-voltage smart-power core, allowing for single-chip integration of signal conditioning, data processing, power management, actuator driving, and line communication functionalities required for industrial applications. Simultaneously, it offers low nonrecurring engineering cost and high design flexibility owning to the utilized gate array technology. In this paper, the SPGA concept is introduced to overcome integration limitations of existing ASIC technologies. Then, design and capabilities of the SPGA functional modules are described. Finally, a practical SPGA application example of single-chip integrated solenoid valve control and monitoring system is demonstrated. [ABSTRACT FROM PUBLISHER]

As inverters are often used in critical applications, reliability is an important issue. In particular, the power electronic switches and gate drivers, the most essential components of the inverter, are vulnerable parts in real live operation. Therefore, this paper focuses on open-switch fault detection for multilevel inverters. When a single-switch open-circuit fault occurs in one of the power electronic switches, the algorithm can detect the fault and the switch that is causing it. The detection is worked out for both a linear resistive inductive load and an induction motor. The proposed algorithm is an extension of an already available finite-set model-based predictive control algorithm. Therefore, no extra hardware or measurements are required. This paper also discusses a suggested method for reconfiguration after fault detection. Computer simulation and experimental verifications validate the proposed methods. [ABSTRACT FROM PUBLISHER]

Connecting legs in parallel in a voltage source inverter is a way to increase the output current and, thus, its rated power. The connection can be made using either coupled or uncoupled inductors, and achieving an even contribution to the output current from all the legs is a crucial issue. Circulating currents produce additional losses and stress to the power devices of the converter. Therefore, they should be controlled and minimized. An efficient technique to attain such balance when coupled inductors are used is presented in this paper. The proposed technique can also be used when the inductors are uncoupled, since it is a particular case where the coupling coefficients are zero. This technique does not include proportional–integral controllers and does not require any parameter tuning either. The exact control action needed to reach current balance is straightforwardly calculated and applied. Experimental results are shown in this paper to verify the efficiency of the proposed balancing method. [ABSTRACT FROM PUBLISHER]

This paper proposes a bidirectional three-phase direct ac–ac converter, with only capacitors and switches in its power circuit and with its operation based on the switched-capacitor principle. The converter presents fixed gain, it keeps the frequencies of the output and input voltages equal, and it operates in open loop with constant switching frequency and duty cycle. The main advantages of the proposed converter are the absence of magnetic elements in the power circuit, the higher efficiency, the higher power density, the higher specific power, the lower cost, and the fact that it can convert ac–ac voltages within a wide frequency range, including dc voltage. Therefore, it is suitable to replace the conventional three-phase autotransformer in industrial, commercial, and residential applications, and it can be designated as a magnetic-less three-phase solid-state autotransformer. The principle of operation, a qualitative and quantitative analysis, the design methodology, and a fabricated example are described in this paper. In order to verify the converter in the laboratory, a prototype with the following characteristics was designed and fabricated: 6 kW, 1.35 kW/kg, 380/110 V, and switching frequency of 100 kHz. The measured efficiency at rated power was 96.3%, and other relevant experimental results are reported herein. [ABSTRACT FROM PUBLISHER]

Silicon carbide Schottky barrier diodes (SiC-SBDs) are prone to electromagnetic oscillations in the output characteristics. The oscillation frequency, peak voltage overshoot, and damping are shown to depend on the ambient temperature and the metal–oxide–semiconductor field-effect transistor (MOSFET) switching rate (dIDS/dt). In this paper, it is shown experimentally and theoretically that dIDS/dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off. As a result, the oscillation frequency and peak voltage overshoot of the SiC-SBD increases with temperature during diode turn-off. This temperature dependence of the diode ringing reduces at higher dIDS/dt and increases at lower dIDS/dt. It is also shown that the rate of change of dIDS/dt with temperature (d^2IDS/dtdT) is strongly dependent on RG and using fundamental device physics equations, this behavior is predictable. The dependence of the switching energy on dIDS/dt and temperature in 1.2-kV SiC-SBDs is measured over a wide temperature range ( -75\ ^\circ\C to 200\ ^\circ\C). The diode switching energy analysis shows that the losses at low dIDS/dt are dominated by the transient duration and losses at high dIDS/dt are dominated by electromagnetic oscillations. The model developed and results obtained are important for predicting electromagnetic interference, reliability, and losses in SiC MOSFET/SBDs. [ABSTRACT FROM PUBLISHER]

This paper illustrates the design and an experimental test of a line-fed solid-state lamp driver based on the asymmetrical half-bridge flyback converter. Its favorable characteristics, in terms of soft-switching range and circuit complexity, allow the converter to operate at variable switching frequency in the range of 300–450 kHz, supplying 6 W to the load with good efficiency. The considered lamp is made up of five series-connected high-power light-emitting diodes (Cree XR-E) and is supplied with 350-mA closed-loop-regulated constant current. While presenting similar complexity and overall efficiency with respect to a conventional driver, due to an original feedforward control technique that allows shrinking the input filter capacitor, the proposed circuit allows a significant volume reduction and consequent power density improvement. [ABSTRACT FROM PUBLISHER]

This paper proposes an analytical procedure for computation of all pairs of valid switching angles used in pattern generation in five-level H-bridge cascaded inverters. The proposed procedure eliminates harmonic components from inverter output voltage and, for each harmonic, returns the exact boundaries of all valid modulation index intervals. Due to its simple mathematical formulation, it can be easily implemented in real time using a digital signal processor or a field-programmable gate array. In this paper, after a detailed description of the method, simulation and experimental results demonstrate the high quality of achievable results. [ABSTRACT FROM PUBLISHER]

In this paper, a novel transformerless interleaved high step-down conversion ratio dc–dc converter with low switch voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive voltage division, the main objectives of the new voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses of active switches. As a result, the proposed converter topology possesses the low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input voltage, 25-V output voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance. [ABSTRACT FROM PUBLISHER]

Although compact fluorescent lamps (CFLs) have been on the market for a long time, many of them do not achieve the same power factor as the incandescent lamps do, which presents a significant problem for the utility with the current widespread use of CFLs for household lightings. A simple single-switch electronic ballast with passive valley-fill power factor correction is proposed in this paper for CFL application. The proposed single-switch ballast circuit is able to achieve zero current switching to maximize the circuit efficiency. A simple feedback circuit with duty ratio control is also proposed to improve the high lamp current crest factor caused by the valley-fill circuit. Detailed descriptions and analysis of the circuit operating principles are provided in this paper. Simulation and experimental results are given on a 13-W CFL tube from Osram Sylvania to highlight the merits of the proposed work. [ABSTRACT FROM PUBLISHER]

Dual-inverter configuration has been attracting increasing attention, especially in motor drives, for its advantages in fault tolerance, multilevel modulation effect, dc voltage utilization, etc. However, its switch fault diagnosis is difficult due to the symmetry of the two sub-inverters. A signal processing approach is proposed in this paper to detect the switch open-circuit fault occurrence and further identify the specific faulty switch, benefiting maintenance and fault-tolerant operation. In this scheme, the faulty phase and the faulty switch pair, consisting of the faulty switch and the switch on its diagonal, are identified using the stator phase currents average values. Following that, the bridge of the faulty phase is forced into a unipolar mode by artificially turning off one switch in the healthy pair continuously. Through properly controlling the duty ratios of the other switches in this bridge, the faulty switch is allowed to be further identified from the faulty pair by analyzing the behavior of the induced current in this phase. This approach is independent of either the speed or the voltage information. The effectiveness is validated through experiments on a sensorless controlled open-end winding induction motor drive. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) has been one of the most popular candidates in high-voltage applications. However, reliability is a critical issue due to a large number of power switching devices and capacitors applied in the MMC. To improve the reliability of the MMC, a fast and reliable diagnosis strategy for the open-circuit fault is proposed in this paper, where submodule voltage sensors are relocated to the upper switching device. Furthermore, a voltage observer based on the submodule voltage sensor is established to monitor the capacitor and realize the power control of the MMC under normal operation. A Boolean logic operation based fault indicator is put forward based on the relationship of the operation state and binaried output of voltage sensors, which could detect and locate the open-circuit faults of the MMC very fast. The ratio of the increment of the observed and measured capacitor voltage during the period of positive arm current is applied to monitor the capacitor. The effectiveness of the proposed fault diagnosis strategy and the capacitor monitoring strategy is verified by the experiment results. [ABSTRACT FROM AUTHOR]

This paper reports the application of silicon bipolar junction transistor (BJT) modeling techniques to the modeling of dynamic behavior of high-voltage 4H-SiC BJTs, and the experimental validation thereof. High-voltage silicon BJTs are impractical due to their low current gain that requires a bulky base driver. Emergence of high-voltage 4H-SiC vertical NPN BJTs with a tenfold higher gain enables the application of efficient drivers, with ratings close to those of IGBTs. This paper demonstrates the advantages offered by 4H-SiC BJTs by means of wide-scale measurements at 800 V and 10 A in a range of temperatures up to 175 °C and adjusted base driver switching rates. This paper shows that the turn-off storage delay in the SiC BJT is two orders of magnitude lower than that of the silicon device. It also shows that the turn-on switching transients of SiC device are by an order of magnitude and the turn-off transients are by two orders of magnitude faster than that of its silicon counterpart, resulting in a tenfold reduction of the switching energy. It also demonstrates the temperature dependence of switching transients of the silicon BJT, and the relative temperature-invariance of the SiC device's performance. This paper concludes with validation of the transient models for the 4H-SiC NPN BJT, showing that the model is sufficiently accurate for transient switching and loss calculations. [ABSTRACT FROM AUTHOR]

Partial discharge (PD) detection is a fundamental tool for the design and diagnosis of insulation systems, particularly organic materials that must operate throughout their life without PD. While the methods for PD measurements under sinusoidal supply voltage are well-established, the same does not hold under repetitive-pulse voltage waveforms, such as those provided by inverters. Electromagnetic noise generated by electronic switch commutation in inverters can overlap with PD pulses, making it difficult to measure, separate from noise, and identify PD. This is particularly more cumbersome when fast rise-time switches are employed. To address these issues, this paper investigates methods to detect PD pulses on enameled wires under repetitive impulsive voltages with different rise times of 60, 500, and 1000 ns, proposing techniques which allow separation of PD from noise even when they overlap in time and frequency domains. This paper employs a time-domain approach using standard deviation curve acquired from a set of measurements to discriminate PD from repetitive commutation disturbance. These techniques can be implemented to achieve unsupervised noise rejection, which would be an important goal for both offline and online PD testing. The proposed approach is validated successfully through tests carried out on a low-voltage motor. [ABSTRACT FROM AUTHOR]