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The five-phase coupled-inductor inverter is a newly proposed option for three-level five-phase inverter drives. This paper comprehensively analyzes the inverter including the coupled-inductor current, current stress on the dc-link capacitors, and a comparison of these performance aspects using three pulse width modulation (PWM) strategies. Mathematical derivations of the inverter currents and the associated current stress reveal that the current stress is not only influenced by the choice of modulation strategy, as in the neutral-point-clamped topology, but also by the value of coupled inductance; furthermore, the choice of the modulation strategy impacts the core loss of the coupled inductors. Three carrier-based PWM methods are considered: sinusoidal PWM (SPWM), and two methods with the common-mode voltage reduction (referred to as CMVR1 and CMVR2) for the five-phase coupled-inductor inverter. CMVR2 is shown to be the best solution if common-mode voltage reduction is required. The analysis demonstrates that SPWM performs better with respect to current stress and inverter losses, therefore is the preferable modulating strategy for the five-phase coupled-inductor inverter if common-mode voltage reduction is not required. The analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Multilevel active neutral-point-clamped (ANPC) converter is popularly known for its higher medium voltage drives up to 6.9 kV. However, common-mode voltages (CMV) are generated when using the well-established carrier-based pulse width modulation (PWM) modulation technique. As a result, CMV will become the major cause of the premature bearing failures and the conducted electromagnetic interferences. In this paper, a reduced CMV strategy is proposed for the ANPC which employs an alternatively new hybrid carrier-based modulation named as interleaved sawtooth carrier phase-disposition PWM (ISC-PD-PWM). By doing so, enhanced harmonic profile is achieved as compared to the typically used classical phase-shifted carrier PWM (PSC-PWM). Therefore, a comparative evaluation of the seven-level (7L) ANPC performance using the proposed reduced CMV approach is made between the novel hybrid ISC-PD-PWM and the conventional PSC-PWM in terms of harmonic analysis. The experimental results have proven the feasibility of the proposed concepts with the CMV effectively reduced. Such perceived merits make ANPC be more attractive for its motor drives. [ABSTRACT FROM AUTHOR]

This paper introduces a combination of two proposed efficiency improvement techniques for a microinverter with current mode control zero-voltage switching output stages. The first technique is dynamic dead-time optimization wherein pulse width modulation dead times are dynamically adjusted as a function of load current. The second method is advanced phase skipping control which maximizes inverter efficiency by controlling power on individual phases depending on the available input power from the photovoltaic source. Neither of the techniques requires any additional circuit components and both can be easily implemented in digital controller firmware. The two techniques were designed and implemented in a 400-W three-phase microinverter prototype. The experimental results validate the theoretical analysis of these techniques and demonstrate that a significant efficiency improvement can be achieved by combining the two proposed control techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a new three-phase modular multilevel inverter (MMLI). The proposed inverter consists of repeated modular primary cells that are connected in series configuration. Therefore, the proposed topology can be extended to get more output voltage levels by adding additional cells without increasing voltage stresses across power switches. Both sinusoidal pulsewidth modulation (SPWM) and staircase modulation are successfully applied to the proposed inverter. The proposed inverter features many advantages such as reduced number of semiconductor power switches, driver circuits, dc-voltage sources, simplified control algorithm, and reduced voltage stresses across the switches independent of output voltage level. Furthermore, the performance of the proposed inverter is studied under both open-loop and closed-loop operations for highly inductive load. Beside the obtained simulation results, a laboratory prototype has been carried out and tested to verify the control techniques and performances of the topology. Simulation and experimental results are compared together to highlight the similarity and consistence of them. [ABSTRACT FROM AUTHOR]

The major drawbacks of classical direct torque control (DTC) are large torque ripples and variable switching frequency. Torque ripples in DTC drives can be attenuated if a three-level inverter is employed instead of a two-level inverter. Nevertheless, torque ripples can still be large if low switching frequencies are used. To alleviate these problems, a constant-switching-frequency-based three-level DTC (3L-DTC) algorithm is presented in this paper. Operating at low, constant switching frequency, the proposed algorithm is effective in reducing torque ripples under all operating conditions. Detailed analysis and design guidelines for the proposed 3L-DTC algorithm are presented. In addition, typical issues associated with the three-level inverter, such as neutral-point voltage fluctuations and smooth voltage vector switching, are addressed. Experimental results are presented to validate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) control of multilevel inverters (MLIs) is very popular. However, it gets extremely challenging with the increase in the number of output voltage levels due to the emergence of subtriangles in the various sectors of the hexagon, which results in increased computational complexity and storage requirements of switching states and corresponding pulse durations. Currently, this is handled through laborios offline computations in conjunction with the visual inspection of the space vector hexagon and its various sectors. This paper aims to simplify the implementation of the SVM scheme for an n-level MLI by proposing generalized equations that not only facilitate direct online computation of control pulses and obviate the requirement of lookup tables but also result in optimized switching. Yet, the on-time computations of the various MLI switches are still based on simple two-dimensional Cartesian co-ordinate system combined with the basic two-level inverter implementation. The proposed scheme makes use of a unique l-factor approach, which directly identifies the location of the various subtriangles in the space vector hexagon and leads to direct online computations of the control pulses. The proposed scheme is validated by simulations and experimental results for three- and five-level diode clamped MLI. [ABSTRACT FROM AUTHOR]

In high-power traction drive systems, the switching frequency of the inverter is strictly limited owing to the restrictions on switching losses and cooling conditions. In this case, the multimode modulation strategy is usually adopted. Based on the analysis of a modified 24-sector space vector pulse width modulation (SVPWM) technique, several synchronous modulation strategies with different pulse numbers are proposed in this paper, which can be applied to the two-level six-phase voltage-inverter-fed asymmetrical dual-stator induction machines. By comparing the harmonic performance of the synchronized modulations, the authors present a set of multimode SVPWM strategy, which is suitable for the high-power traction drive systems under low switching frequency. At the same time, the switching strategy for transitions between different modulation modes is proposed as well. Simulation and experimental results verify the validity and effectiveness of the proposed synchronized modulation strategies and the switching strategy between different modulation modes. [ABSTRACT FROM AUTHOR]

Multiterminal converters eliminate using several single-input-single-output converters and simplify their topologies and reduce their cost. In this paper, a new family of multi-input converters based on three switches leg is introduced. Inputs of the proposed converters are similar and they are topologically interchangeable and have boost or buck operation modes. The proposed converter has one output that operates as an inverter. Here, all operating modes of the proposed converters and their effects on each other are investigated, in details. Also, an appropriate switching technique for the converters is given. A detailed comparison between conventional and proposed two-input converters is also presented. A two-input, one-output prototype converter has been implemented to validate the given analyses and to verify the proposed converter's performance. The experimental results are in good agreement with the theoretical and simulated analyses. [ABSTRACT FROM AUTHOR]

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory. [ABSTRACT FROM AUTHOR]

This paper presents a finite-control-set model predictive control (FCS-MPC) for grid-tied packed U cells (PUC) multilevel inverter (MLI). The system under study consists of a single-phase 3-cells PUC inverter connected to the grid through filtering inductor. The proposed competitive topology allows the generation of 7-level output voltage with reduction of passive and active components compared to the conventional MLIs. The aim of the proposed FCS-MPC technique is to achieve, under various operating conditions, grid-tied current injection with unity power factor and low total harmonic distortion while balancing the capacitor voltage. Parameters’ sensitivity analysis was also conducted. The study is conducted on a low-power case study single-phase 3-cells PUC inverter and with possible extension to higher number of cells. Theoretical analysis, simulation, and experimental results are presented and compared. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid selective harmonic mitigation (SHM)-selective harmonic elimination (SHE) switching technique based on pulse-amplitude modulation (PAM) concept. It has been applied on a four-leg neutral-point-clamped (NPC) inverter to eliminate and mitigate more harmonic orders than recently proposed hybrid SHM-SHE-pulse width modulation (PWM) method while generating switching pulses at the same frequency. In conventional SHE and SHM techniques, equations are solved to attain the switching angles. Regarding the PAM, value of inverter dc voltage can be considered as an additional degree of freedom by which the flexibility of such techniques would be increased maintaining the switching frequency. In the proposed SHM-SHE-PAM, the conventional equations are reformulated to obtain constant switching angles for a vast range of modulation index (ma) applied on a four-leg NPC inverter. Switching pulses of the three-phase legs and the fourth leg are calculated to mitigate the nontriplen harmonics and eliminate the triplen ones, respectively. Due to the unique switching angles valid in the whole range for ma, the calculation time and volume (storage capacity) are significantly reduced leading to a simpler controller implementable on a low-risk and cheap AVR chip. Experimental tests’ results of a four-leg NPC inverter as UPS application prove the good dynamic performance and accuracy of the proposed implemented switching technique in producing associated pulses for the inverter switches at very low frequency to mitigate/eliminate undesired harmonic orders from the output phase/line voltage waveforms without using bulky filters. [ABSTRACT FROM AUTHOR]

This paper presents a new E-type module for asymmetrical multilevel inverters (MLIs) with reduced components. Each module produces 13 levels with four unequal dc sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and dc sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge, which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high-quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output. [ABSTRACT FROM AUTHOR]

A new single-phase \uppi-\texttype 5-level inverter using 3-terminal switch-network (3TSN) is proposed in this paper. The topology is considered as a variant of T-type 3-level structure or dual-buck inverter with coupled inductors. This new inverter is suitable for multilevel power inversion with low dc-bus voltage. The merit of the proposed topology is to apply only four active power switches to achieve 5-level operation. Other benefits include double frequency operation of output inductor and equal division of the current that flows through power switches and filter inductor. Hence, it leads to high efficiency and low harmonics. These characteristics allow improvement of losses distribution and volume reduction of output filter inductor. The operation scenario with sinusoidal pulsewidth modulation (SPWM) is described in details. Meanwhile, the magnetic analysis and design are studied and discussed. Finally, a prototype is built to verify the theoretical analysis and demonstrate the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

Multilevel converters have received more attention recently. Multilevel converters can be used not only in high-voltage high-power applications, but also in energy storage systems, thanks to reduced harmonics and electromagnetic interferences. State-of-charge (SoC) balancing of the storage system cells within cascaded multilevel inverters, e.g., batteries, can be one of the challenges in practical applications. Different methods have been studied and reported in technical literature. However, the SoC balancing is still a challenging issue. In this paper, a new method is proposed to solve this problem by applying several clever but simple changes to the staircase modulation switching scheme without changing the output waveform properties. Validations for this simple method were performed through simulation and experimental prototype. Despite the simplicity of the method, the simulation and experimental results show that SoC balancing of the cells has significantly improved. [ABSTRACT FROM PUBLISHER]

The performance of Voltage Source Inverter (VSI) is affected by power semiconductor nonlinearities, dead time, and control delay. The compensation of these nonlinear effects is necessary to meet requirements in terms of current quality and high efficiency, especially for grid-connected power conversion systems. In this paper, the effects of nonlinearities are widely analyzed and a new compensation technique for a steady-state current-controlled VSI is proposed. It is based on a step-by-step voltage compensation on the basis of the current error evaluated within each control interval. As a result, a complete compensation is achieved within a whole period of the fundamental. To cope with the zero-current clamping effect, the proposed compensation technique is implemented in a recursive way. For slow-dynamic applications, such as photovoltaic systems, this method allows achieving high performance with very low computational requirements. [ABSTRACT FROM PUBLISHER]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a unified PWM method for matrix converters so as to establish a common platform which can generate various types of PWM methods in real time by adjusting the free parameters in the modulation algorithm. As a foundation for unification, the general form of the modulation functions for matrix converters is derived using geometric transformation approach. All eligible direct modulation matrices are shown to be of indirect form and are expressed in terms of instantaneous phase quantities. This paper also presents a new viewpoint to consider a matrix converter as a generalized three-level inverter and to apply the double-carrier-based dipolar modulation technique of the three-level inverter to the matrix converter. Several concepts of the two-level PWM inverters are then generalized to the matrix converters for better visualization and understanding of the modulation process. [ABSTRACT FROM AUTHOR]

In this paper, total harmonic distortion (THD) minimization of the output voltage of multilevel inverters is discussed. An efficient approach in reducing the harmonic contents of the inverter's output voltage is THD minimization. In multilevel inverters with a fundamental frequency switching strategy (each switch turning on and off once per output cycle), the switching angles can be selected so that the output THD is minimized (such as the so-called optimal-minimization-of-THD strategy). To obtain the optimum switching angles, an optimization algorithm is applied to the output-voltage THD. In three-phase multilevel inverters, the optimization algorithm is commonly applied to the phase voltage of the inverter. This results in the minimum THD in phase voltage but not necessarily in the line-to-line minimum THD, whereas in three-phase applications, the line-voltage harmonics are of the main concern from the load point of view. In this paper, using the genetic algorithm, a THD minimization process is directly applied to the line-to-line voltage of the inverter. This paper is based on a seven-level inverter. To verify the simulation results, a seven-level-cascaded-H-bridge-inverter-based hardware prototype, including an ATMEGA32 AVR microcontroller, has been implemented. Both simulation and experimental results indicate superiority of this approach over the commonly used phase-voltage THD minimization approach. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

Flux harmonic distortion factors (HDFs) of two space vector pulse width modulation (SVPWM) schemes, aimed at sinusoidal output voltage generation with five-phase voltage source inverters, have been evaluated in Part 1 of this paper. Analytical considerations and numerical integration have been applied in order to determine the switching properties of the considered SVPWM methods. It has been shown that the SVPWM based on four large vectors leads to a considerably higher overall per-phase flux HDF than the method based on two large and two medium space vectors. The purpose of the second part of the paper is to relate flux HDFs to the current ripple and current total harmonic distortion and thus explore further switching characteristics of the two SVPWM techniques. The applied approach is based on simulation and experimentation, in conjunction with the subsequent fast Fourier transform of the waveforms, so that all the results for the ripple are obtained using a methodology completely different from the one in Part 1. Relationships that correlate the current ripple and the flux HDFs are established, and it is further shown that the current ripple can be easily calculated from the flux HDF values of Part 1 if the relevant leakage inductances of the two planes are known. Hence, the complete theory of Part 1 is fully verified by both simulation and experimentation. It is also shown that, in certain cases, the SVPWM based on four large vectors may lead to a smaller current ripple despite a considerably higher flux HDF. [ABSTRACT FROM AUTHOR]

Multiphase variable-speed drives supplied from two-level voltage source inverters (VSIs) are, at present, contenders for numerous industrial applications. Various pulsewidth modulation (PWM) methods for multiphase VSIs, aimed at sinusoidal output voltage generation, have been developed using both carrier-based and space-vector approaches. An increased number of voltage space vectors, available for the synthesis of the output voltage, offer greater flexibility for the PWM scheme development, compared to the three-phase case. This paper presents comprehensive analytical analysis and comparison of switching ripple characteristics of two continuous space vector PWM (SVPWM) methods for a five-phase two-level VSI. Considered SVPWM schemes select a different set of four active space vectors per switching period in order to generate sinusoidal output voltages. This paper also presents the evaluation of the flux harmonic distortion factors of the SVPWM techniques. Correlation with corresponding current ripple and total harmonic distortion is established in Part 2 of this paper, where theoretical considerations are verified by simulations and through experimental investigation on a five-phase VSI-fed induction motor drive. [ABSTRACT FROM AUTHOR]

The main objective of this paper is to simplify the implementation of continuous and discontinuous 3-D space vector pulsewidth modulations (SVPWMs). This paper analyzes the relationships, whether in abc or \alpha\beta 0 coordinates, between three-phase voltages and the following elements: the tetrahedron in which the reference vector resides, three adjacent active switching vectors (or three switching states), and their duration times. Based on the analysis, the calculation of the turn-on time of each switch in the actual implementation is simplified, and discontinuous PWM (DPWM) methods in three-leg inverters can be extended to four-leg inverters without the phase angle. In addition, two more DPWM methods that are peculiar to 3-D SVPWM are presented. This simplified algorithm does not use irrational operations or look-up tables, and it alleviates the computation burden of the processor. The simulation and experimental results are provided to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

In this paper, the detection and isolation of open-switch faults in induction motor (IM) drives are addressed from a model-based perspective. Residuals are synthesized by using nonlinear observers followed from a directional characterization. First, it is observed that the IM model can be written in a recurrent decoupled structure by taking the stator currents and mechanical velocity as outputs. In this way, residuals can be insensitive to load torque and operating conditions, and simultaneous faults can be addressed. A pulsewidth modulation three-phase inverter is studied as power actuator for the IM. Hence, in order to isolate faults related to the six switching devices, a directional residual evaluation in the dq-frame is employed. Hence, three residuals are constructed to isolate the faulty switches. The ideas presented in this paper are validated experimentally in a test bench of 1-hp IM under single and simultaneous faults. [ABSTRACT FROM AUTHOR]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]

This paper presents a model predictive control (MPC) scheme for quasi-Z-source (qZS) three-phase four-leg inverter. In order to cope with the drawbacks of traditional voltage source inverters (VSIs), a qZS three-phase four-leg inverter topology is proposed. This topology features a wide range of voltage gain which is suitable for applications in renewable energy-based power systems, where the output of the renewable energy sources varies widely with operating conditions such as wind speed, temperature, and solar irradiation. To improve the capability of the controller, an MPC scheme is used which implements a discrete-time model of the system. The controller handles each phase current independently, which adds flexibility to the system. Simulation and experimental studies verify the performances of the proposed control strategy under balanced and unbalanced load conditions as well as single-phase open-circuit fault condition. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to present a new structure for switched-capacitor multilevel inverters (SCMLIs) which can generate a great number of voltage levels with optimum number of components for both symmetric and asymmetric values of dc-voltage sources. The proposed topology consists of a new switched-capacitor dc/dc converter (SCC) that has boost ability and can charge capacitors as self-balancing by using the proposed binary asymmetrical algorithm and series–parallel conversion of power supply. The proposed SCC unit is used in new configuration as a submultilevel inverter (SMLI) and then, these proposed SMLIs are cascaded together and create a new cascaded multilevel inverter (MLI) topology that is able to increase the number of output voltage levels remarkably without using any full H-bridge cell and also can pass the reverse current for inductive loads. In this case, two half-bridge modules besides two additional switches are employed in each of SMLI units instead of using a full H-bridge cell that contribute to reduce the number of involved components in the current path, value of blocked voltage, the variety of isolated dc-voltage sources, and as a result, the overall cost by less number of switches in comparison with other presented topologies. The validity of the proposed SCMLI has been carried out by several simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a new topology for half-bridge switched boost inverter (HB-SBI) is proposed. The proposed half-bridge inverter uses more active elements rather than capacitors and inductors in comparison with the conventional half-bridge Z-source inverter with two Z-networks, which results in reduction of weight, size, and cost. Moreover, the proposed inverter has the capability of eliminating inverter leg short-circuit issues and is able to further increase the output voltage level in comparison with its conventional types. Generating zero-level output voltage is also another advantage of this topology. Based on theoretical calculations, the steady-state and small-signal analysis of the proposed topology in different operating modes are performed and the ripple of inductors’ current and capacitors’ voltage are also calculated. A comprehensive comparison is also made between the proposed inverter and the conventional types. Finally, the experimental results are provided to reconfirm the performance of the proposed inverter. [ABSTRACT FROM PUBLISHER]

Modular multilevel converter (MMC) is a promising new topology for high-voltage applications. The MMC is made of several identical submodules. For proper operation, each submodule can be considered as a controlled voltage source where capacitor’s voltage should be maintained at a certain level. Besides, the minimization of the circulating current, which does not flow to the load, is crucial for achieving stable and efficient operation of the MMC. The interrelations among the load current, circulating current, and capacitor voltages complicate the MMC control. This paper aims to achieve stable and balanced voltage and current control with reduced circulating current in various operating conditions. The proposed control uses weighted model predictive control based on a normalized cost function to select the inverter switching patterns, which control the load current, while minimizing voltage fluctuation and circulating current. The weighting factors were selected based on minimizing the load-current total harmonic distortion (THD) and circulating current. The analysis is conducted on a low-power case study of single-phase four-cells MMC with possible extension to higher number of cells. The low-power three-level prototype is designed and built to validate this proposed method. Theoretical analysis, simulation, and experimental results are presented and compared. Parameter sensitivity analysis was also conducted. They all confirm the effectiveness of the proposed control method. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence currentin the motor phases, which is caused by the existence of zero-sequence voltage in them. The other is the overcharging of the dc-link capacitor of theinverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of aspecial variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which arectifier–inverter combination is nested within the conventional two-level inverter configuration to achieve four-level inversion. This PWM schemeis named as the sample-averaged zero-sequence elimination (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling timeperiod in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configurationby resorting to the proposed SVPWM strategy. [ABSTRACT FROM PUBLISHER]

This paper presents proportional integral direct torque control (PIDTC) and fuzzy-2 DTC (F2DTC) of the induction motor (IM) drive using space vector pulse width modulation (SVPWM) for three-level diode-clamped inverter (TDCI). The above control schemes have been implemented in the laboratory using 2 HP IM through a DSPACE DS-1104 controller. The control schemes are capable to balance the dc-link capacitor voltages of TDCI by selecting an optimum voltage vector without using an extra controller. However, the three-level PIDTC of an IM gives poor transient performance during starting, loading, and speed reversal with considerable current and voltage total harmonic distortion (THD). In addition, it takes more time to reach the steady state with large spikes on capacitor voltages during the load or speed variation. This is due to poor performance of the PI controllers (speed and torque). In F2DTC, the conventional PI controllers are replaced by Mamdani-type fuzzy-2 controllers using a centroid method with simple logical rules. The simulated and experimental performance show that F2DTC for the three-level inverter-fed IM drive provides a fast dynamic response, less current and voltage THDs, considerable less distortion in flux and torque, and fewer spikes on capacitor voltages as compared to PIDTC. [ABSTRACT FROM PUBLISHER]

In an electric drive vehicle (EDV), the available voltage on a dc-link is limited, and so the inverter output voltage and, consequently, the line motor maximum speed are limited. The fundamental voltage of the inverter output is increased approximately 27% using a square wave (SW) switching pattern instead of a sine wave switching pattern. However, this pattern can only be used at high speeds, and at lower speeds a pulsewidth modulation (PWM) pattern should be used. In order to achieve proper control, the switching pattern should be changed seamlessly. In the present paper, a new PWM scheme for single-mode seamless control of Vernier motors is proposed. In the proposed scheme, the reference voltage is modified to change the switching pattern continuously so that the voltage changes smoothly from a high-frequency pattern to an SW and voltage discontinuity does not occur. Experimental results reveal that the inverter-switching pattern changes smoothly from a sinusoidal PWM pattern to an SW pattern, and so seamless control from the constant-torque region to the constant-power region, and vice versa, is achieved. Since the proposed scheme is a single-mode control, it is much simpler than current technologies, which are based on multimode controllers. Also the proposed method has a lower total harmonic disturbance (THD) as well as a lower harmonic distortion factor (HDF) compared to some existing methods. [ABSTRACT FROM PUBLISHER]

Multilevel inverters are gaining more attention in ac drive application due to their many attractive features. In the case of conventional neutral-point-clamped (NPC) or flying capacitor multilevel inverter configurations, active switches are connected in series to produce multilevel output voltage waveform. Therefore, if any one switch fails, the entire configuration has to be shut down; this will reduce the reliability of the system. A dual three-level inverter configuration for induction motor drive is proposed in this paper to improve reliability of the system. This topology is developed by feeding four-pole induction motor stator winding with four conventional two-level inverter modules. A level-shifted carrier-based third harmonic injection pulsewidth-modulation technique is used to produce the gating signals for the proposed configuration. By providing proper phase shift between carrier waves, multilevel voltage waveform is produced across the total motor phase winding, and first center band harmonics are also canceled. Thereby, the torque ripple will be considerably reduced compared with conventional NPC five-level inverter-driven induction motor drive. Finite-element analysis (FEA) is used to estimate the torque ripple when induction motor is supplied by the proposed configuration and conventional five-level NPC inverter configuration to show the effectiveness of the proposed converter. The proposed configuration is simulated using MATLAB/Simulink and experimentally verified using a laboratory prototype with a 5-hp four-pole induction motor drive. [ABSTRACT FROM PUBLISHER]

This paper describes a single-phase full-bridge inverter that possesses limited current ripple at the dc link while providing a sinusoidal square power at the ac output. This is achieved through the addition of an extra pair of switches and complementary control for the full-bridge inverter. The extra switches operate to prevent the double-line frequency ripple current from flowing into the input of the inverter. In doing so, the pulsation component of the sinusoidal square output power is confined to flow between the output capacitors and the load. Thus, the dc link input only supplies the dc component of the output power. Simulation and experimental results validating the proposed solution are presented. [ABSTRACT FROM PUBLISHER]

In this paper, a novel grid-connected high step-up inverter is proposed. The topology is composed of two stages. The first stage is a single-switch high step-up dc–dc converter with bipolar outputs, and the second stage is a conventional half-bridge dc–ac grid-connected inverter. Negative grounding of the photovoltaic (PV) module has resulted in elimination of unwanted ground leakage currents in the PV system. Simple structure, employing few semiconductor switches, simple control, and high efficiency are the features of the proposed topology. Theoretical analysis and principal operation of the circuit are discussed. An experimental prototype is implemented to verify the performance of the proposed inverter. The experimental results confirm the aforementioned features and the theoretical analysis of the converter operation. [ABSTRACT FROM PUBLISHER]

This paper presents a sliding-mode control (SMC) strategy for single-phase grid-connected \mboxLCL-filtered voltage source inverters (VSIs) with double-band hysteresis scheme. The proposed SMC is simpler than the existing SMC methods devised for grid-connected VSIs since its sliding-surface function requires the sensing of capacitor voltage and grid current only. In addition, a double-band hysteresis scheme which ensures the switching of a transistor in the VSI during a half cycle while it remains either on or off in the other half cycle of the fundamental period is used to mitigate the switching frequency. Furthermore, the analytical expressions for the instantaneous and average switching frequencies are derived. The theoretical considerations and analytical results are verified through computer simulations and experimental results obtained from a 3.3-kW system. Simulation and experimental results show that the proposed SMC strategy exhibits an excellent performance in achieving the required control objectives such as fast dynamic response, robustness, sinusoidal grid current with low total harmonic distortion, and simplicity in a practical implementation. [ABSTRACT FROM PUBLISHER]

This paper proposes a new topology for an enhanced-boost Z-source inverter (ZSI) with combined two Z-impedance networks. By two Z-impedance networks and low shoot-through duty cycle, the proposed inverter produces high output voltage gain. In traditional ZSIs for high boosting voltage, a low modulation index is required; hence, under these conditions, the output voltage will have low quality with high total harmonic distortion. Compared with the conventional high-boost ZSI topologies, the proposed inverter uses shorter shoot-through duration and a larger modulation index to improve the output waveform quality. Comparison between the proposed topology and previously proposed schemes, in terms of inductor numbers, voltage and current stresses on elements, sizes of inductors and capacitors, efficiency, and switching device product (SDP) factors of diodes, is made, and the results verify the priority of the proposed topology. The operating principle of the proposed topology is analyzed in detail. Both simulation and experimental results verify the high performance of the proposed inverter. [ABSTRACT FROM PUBLISHER]

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the d_2-q_2 vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the d_2-q_2 vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques. [ABSTRACT FROM AUTHOR]

This paper presents the establishment and operation control of a dc microgrid incorporating with electric vehicle (EV) as movable energy storage. The developed microgrid consists of a wind permanent-magnet synchronous generator ac source and a dc source, a battery/supercapacitor (SC)/flywheel hybrid energy storage system, and a grid-connected bidirectional single-phase three-wire (1P3W) load inverter. Various harvested ac and dc sources can be plugged into the microgrid via the developed interfaced power converters. In addition to good microgrid operation performance, the microgrid-to-grid and grid-to-microgrid operations can be successfully conducted with good power quality. As to the developed EV interior permanent-magnet synchronous motor drive, the SC auxiliary storage is equipped to assist the main battery source in intermittent energy conversion. Satisfactory acceleration/deceleration/reversible and regenerative braking operation characteristics are obtained via the developed power stages and control schemes. Moreover, the successful microgrid-to-vehicle and vehicle-to-microgrid interconnected operations of EV and microgrid are achieved. In addition, the vehicle-to-grid/grid-to-vehicle operations can be also performed via the developed 1P3W inverter. [ABSTRACT FROM AUTHOR]

Hysteresis model predictive control (HMPC) is a variant of finite-control-set model predictive control, which is mainly developed for high-power applications. In this paper, the HMPC scheme is proposed to control a high-power grid-connected two-level voltage source inverter with an inductive-capacitive-inductive (LCL) filter. To ensure the stable operation of the control system, the resonance characteristics of the system with an LCL filter based on HMPC are analyzed, and an active damping scheme is then given. On the other hand, the impacts of the modeling error on system stability and average switching frequency are analyzed in detail. Then, a new switching frequency-adaptive control scheme that uses the average switching frequency to adjust the parameter value of the predictive model online is presented. The new control scheme can keep the average switching frequency within an acceptable operational margin, while improving the stability of the control system. For demonstration, the proposed control scheme has been implemented on a small-scale grid-connected inverter system, and the results show that the theoretical analysis is correct and that the proposed control scheme is effective. [ABSTRACT FROM AUTHOR]

In this paper, a modified zero-voltage-switching pulsewidth-modulation inverter with a digital-signal-processor-based proportional–integral–derivative (PID)-like fuzzy controller (PIDFC) is implemented. The switches of the inverter can achieve a soft-switching feature that can largely reduce switching losses and improve the converting efficiency. In order for the online control of the proposed dc–ac inverter to be feasible, a fuzzy control is designed to be a PID-like fuzzy mechanism with the complexity significantly reduced. From the results, it is shown that the PIDFC can not only stabilize the output at 110 V rms but can also improve the performance when the system load has been changed from 600 to 100 $\Omega$. Comparing with a traditional PID controller, the responding speed can be improved by 75% in the simulation, and the speed can still be improved by 35% in the practice experiment. [ABSTRACT FROM AUTHOR]

Carrier-based pulsewidth-modulation (CBPWM) techniques are popular due to their simplicity, and have been widely researched for various three-phase inverter configurations. In this paper, two CBPWM techniques are proposed to reduce the common-mode (CM) voltage generated by the five-phase inverter. The five-phase inverters have more flexibility in reducing the CM voltage than their three-phase counterparts because they have more phase legs, hence finer control over the star-point voltage of the load. Two methods are proposed for the conventional two-level five-phase inverter to reduce the CM voltage; one utilizing adjacent modulating waveforms and the other utilizing nonadjacent modulating waveforms. The coupled inductor inverter (CII) uses coupled inductors to generate multilevel outputs. As the volt-second balance must be maintained across each coupled inductor, direct application of the proposed methods on the CII inverter will result in overcurrents in the coupled inductors. Hence, the proposed methods are further improved to ensure the volt-second integral over each switching period is zero. Moreover, the two proposed methods are designed to reduce switching events and prevent unexpected states occurring during the switching transitions. The performance and the switching strategy of both methods are verified by both simulations and experiments on a prototype of five-phase CII. [ABSTRACT FROM AUTHOR]

Multiphase machines are well known for their fault-tolerant capability. Star-connected multiphase machines have fault tolerance in an open circuit. For an inverter switch short-circuit fault, it is possible to keep a smooth torque of a permanent magnet synchronous machine if the currents of the faulty phases are determined and their values are acceptable. This paper investigates fault-tolerant operations of an open-end five-phase drive, i.e., a multiphase machine fed with a dual-inverter supply. Inverter switch short-circuit fault is considered and handled with a simple solution. Original theoretical developments are presented. Simulation and experimental results validate the proposed strategy. [ABSTRACT FROM AUTHOR]

In this paper, a fault-tolerant single-phase five-level inverter configuration is proposed for photovoltaic (PV) generation systems. Conventional two-level inverters are popularly used in PV applications, but these inverters provide the output voltage with considerable harmonic content. One of the efficient ways to improve the power quality of PV generation systems is to replace a two-level inverter with a multilevel inverter. Conventional multilevel inverters reduce total harmonic distortion and filter requirements effectively, but it has limitations in terms of reliability due to increased device count and capacitor voltage balancing issues. Therefore, a fault-tolerant single-phase five-level inverter is presented, which is constructed by using a half-bridge two-level inverter, a three-level diode clamp inverter, and a bidirectional switch. The proposed inverter topology can tolerate the system faults due to failure of the source and/or switching devices with least modification in the switching combinations. It has less number of switching devices compared to conventional five-level inverters. The topology also has the energy-balancing capability between sources which helps in reducing uneven charge of batteries in case of partial shading or hotspots on one side of the PV panels. The proposed system under normal and faulty condition is simulated in MATLAB/Simulink environment, and results are verified with a laboratory prototype. [ABSTRACT FROM PUBLISHER]