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This paper discusses the design, implementation, experimental validation, and performances of a field-programmable gate array (FPGA)-based real-time power converter failure diagnosis for three-leg fault tolerant converter topologies used in wind energy conversion systems (WECSs). The developed approach t minimizes the time interval between the fault occurrence and its diagnosis. We demonstrated the possibility to detect a faulty switch in less than 10 [micro]s by using a diagnosis simultaneously based on a 'time criterion' and a 'voltage criterion.' To attain such a short detection time, an FPGA fully digital implementation is used. The performances of the proposed FPGA-based fault detection method are evaluated for a new fault tolerant back-to-back converter topology suited for WECS with doubly fed induction generator (DFIG). We examine the failure diagnosis method and the response of the WECS when one of the power switches of the fault tolerant back-to-back converter is faulty. The experimental failure diagnosis implementation based on 'FPGA in the loop' hardware prototyping verifies the performances of the fault tolerant WECS with DFIG. Index Terms--Diagnosis, fault tolerant, field-programmable gate array (FPGA), wind energy conversion system (WECS).

In photovoltaic systems, dc–dc converters have been identified as one of the most critical and challenging subsystem in terms of failure rate. Thus, this paper proposes fault-tolerant operation of a two-stage buck/buck–boost converter under open-circuit switch failure. Remedial actions are efficient in any failure of one of the two switches of the converter. Here, a new unified approach is considered, for the overall fault-tolerant operation of the two stages of the converter. The fault-tolerant circuit we propose lies on performing redundancy by implementing the equivalent synchronous switch for the two main switches of the two stages, in offline mode. The fault-tolerant circuit results from the basic two-stage buck/buck-boost converter and its equivalent circuit with a synchronous switch, merged together to form the new dc–dc fault-tolerant circuit. Therefore, postfault operation at full power can also be performed. By using a switch fault management unit with reduced complexity, inserted between the control block and the switches, we have designed an unified, efficient, and optimized fault-tolerant control, suitable in both healthy and postfault operations. Some selected experimental tests, which all confirm the good performances of the proposed fault-tolerant approach, are presented and discussed. [ABSTRACT FROM AUTHOR]

The increased penetration of photovoltaic (PV) systems in different applications with critical loads such as in medical applications, industrial control systems, and telecommunications has highlighted pressing needs to address reliability and service continuity. Recently, distributed maximum power point tracking architectures, based on dc–dc converters, are being used increasingly in PV systems. Nevertheless, dc–dc converters are one of the important failure sources in a PV system. Since the semiconductor switches are one of the most critical elements in these converters, a fast switch fault detection method (FDM) is a mandatory step to guarantee the service continuity of these systems. This paper proposes a very fast FDM based on the shape of the inductor current associated to fault-tolerant (FT) operation for boost converter used in PV systems. By implementing fault diagnosis and reconfiguration strategies on a single field-programmable gate array target, both types of switch failure (open- and short-circuit faults) can be detected, identified and handled in real time. The FDM uses the signal provided by the current sensor dedicated to the control of the system. Consequently, no additional sensor is required. The proposed FT topology is based on a redundant switch. The results of hardware-in-the-loop and experimental tests, which all confirm the excellent performances of the proposed approach, are presented and discussed. The obtained results show that a switch fault can be detected in less than one switching period, typically around 100 ms in medium power applications, by the proposed FDM. [ABSTRACT FROM PUBLISHER]

Fault detection (FD) in power electronic converters is necessary in embedded and safety critical applications to prevent further damage. Fast FD is a mandatory step in order to make a suitable response to a fault in one of the semiconductor devices. The aim of this study is to present a fast yet robust method for fault diagnosis in nonisolated dc–dc converters. FD is based on time and current criteria which observe the slope of the inductor current over the time. It is realized by using a hybrid structure via coordinated operation of two FD subsystems that work in parallel. No additional sensors, which increase system cost and reduce reliability, are required for this detection method. For validation, computer simulations are first carried out. The proposed detection scheme is validated on a boost converter. Effects of input disturbances and the closed-loop control are also considered. In the experimental setup, a field programmable gate array digital target is used for the implementation of the proposed method, to perform a very fast switch FD. Results show that, with the presented method, FD is robust and can be done in a few microseconds. [ABSTRACT FROM PUBLISHER]

In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital control schemes on a single FPGA is realized, based on a suited methodology for rapid prototyping. FPGA in loop and also experimental tests are carried out, and the results are presented. These results confirm the capability of the proposed reconfigurable control and fault-tolerant structure. [ABSTRACT FROM PUBLISHER]

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable controller, and fault detection scheme. For experimental tests, the control and the fault detection and reconfiguration schemes are implemented on a single field-programmable gate array (FPGA) chip. Experimental and simulation results show the effectiveness of the proposed fault-tolerant topology and its FPGA-based control. [ABSTRACT FROM PUBLISHER]

This paper presents a top-down design flow for design, implementation, and verification of digital controllers associated with electrical systems. In the proposed design flow, the functional description of the studied system and the detailed electronic hardware design and validation of the digital controller are performed using a hardware-in-the-loop (HIL)-based reconfigurable platform in a unique design environment. The way of using this design flow and the reconfigurable HIL platform is analyzed through a fault-tolerant shunt active power filter application. The experimental results obtained with a laboratory prototype fault-tolerant active filter demonstrate the performances and the efficiency of the proposed design flow and HIL-based reconfigurable platform. [ABSTRACT FROM AUTHOR]