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The cascaded H-bridge converter (CHB) is a very suitable solution with inherent modularity for many applications such as flexible ac transmission systems and motor drives. In this article, the discontinuous pulsewidth modulation (DPWM) by clamping some power cells is used in the CHB because it permits to reduce the switching losses in the power devices. However, this provokes a high harmonic distortion (basebands and sidebands harmonics) in the CHB output voltage compared with the quality obtained avoiding to clamp cells, just applying the conventional phase-shifted PWM (PS-PWM) technique. This has been studied for the three-cell CHB topology but the extension for an N-cell CHB with several clamped cells is a challenge that is addressed in this article. A generalized CHB harmonic voltage analysis applying the DPWM method is presented considering multiple clamped cells. The harmonic distortion mitigation target can be decoupled into two objectives. The proposed method cleverly groups the cells (one clamped + one or two nonclamped cells) to mitigate the basebands harmonic distortion. Simultaneously, a variable-angle PS-PWM technique is applied to the CHB in order to mitigate the sidebands harmonics content. Experimental results demonstrate the good performance of the proposed method. [ABSTRACT FROM AUTHOR]

Modular converters such as the multilevel cascaded H-bridge (CHB) are an attractive option for multiple applications mainly because of inherent modularity and fault-tolerant operation. This article is focused on the CHB converter operating with unbalanced conditions (different dc voltages and/or modulation indexes). Under these circumstances, applying the conventional control and modulation strategies, the output voltage harmonic spectrum is degraded. In this article, a generalized variable-angle phase-shifted pulsewidth modulation (PS-PWM) technique for CHB converters with a large number of power modules (> 3) is presented. The method considers all possible cells’ combinations to form groups and assigns the role of each cell in the group. This cell role defines the identifier of the cell in the variable-angle PS-PWM technique. In the steady state, in each group of cells, the harmonic distortion of the CHB output voltage located at twice the carrier frequency ƒc is eliminated, while the distortion at 4ƒc is also diminished. Experimental results show how the proposed technique achieves superior harmonic performance without introducing any significant disadvantage. [ABSTRACT FROM AUTHOR]

A direct speed control strategy based on finite control set model predictive control (FCS–MPC) with a voltage smoother is presented herein. In the proposed concept, a finite set of smoothed voltage vectors characterized by an adjustable amplitude and a movable origin is introduced as voltage candidates in the FCS–MPC scheme. The controller predicts the future current and speed and outputs the optimal smoothed voltage using pulse-width modulation. Owing to this control scheme, an abrupt change in the output voltage, which causes a large current ripple, is avoided without additional computational costs. Simulation and experimental results obtained using a permanent magnet synchronous motor fed by a two-level three-phase inverter show that the proposed method effectively reduces the current ripple while achieving a high dynamic drive compared with the conventional FCS–MPC scheme. [ABSTRACT FROM AUTHOR]

Deadbeat-direct torque and flux control (DB-DTFC) significantly improves the torque response performance compared with the conventional direct torque control. However, the existing DB-DTFC algorithm suffers from a relatively heavy computational burden due to its intricate derivation. Thus, two simplified DB-DTFC algorithms for permanent magnet synchronous machines (PMSMs) are proposed in this article to relieve the burden. The first one is based on the stator flux differential, and the second one is based on the complex power of PMSM. Furthermore, the performance of DB-DTFC highly relies on the accuracy of machine parameters. Thus, modified stator flux observer and electromagnetic torque observer are designed to enhance parameter robustness based on disturbance observer theory. The theoretical derivation of the proposed methods is investigated in-depth. Finally, both simulation and experimental results verify that the proposed deadbeat methods can maintain the deadbeat performances with a reduced computational burden. Meanwhile, the modified observer can help the deadbeat algorithms work well when machine parameters change. [ABSTRACT FROM AUTHOR]

This article proposes and studies different sigma–delta ($\Sigma$ $\Delta$) modulation strategies for obtaining a constant common-mode voltage (CMV) by eliminating the CMV level transitions in a five-phase voltage source inverter (VSI). These techniques are based on choosing vectors that generate a constant CMV with values of 0.1 $V_{\text{dc}}$ or –0.1 $V_{\text{dc}}$. Because of the high-switching frequencies used with wide-bandgap semiconductors, pulse-width modulation techniques continually generate high dv/dt values. Therefore, the proposal to combine a $\Sigma$ $\Delta$ modulation strategy with vector selections achieves a constant CMV level due to the elimination of its level transitions, a reduction in conducted electromagnetic interference and a high-efficiency converter operation. The average number of switching per transistor of the VSI is analyzed using the results from MATLAB/Simulink and PLECS simulations. Experimental results are obtained by applying the proposed $\Sigma$ $\Delta$ modulation strategies on a VSI with silicon carbide MOSFETs. The results demonstrate the achievement of the aforementioned features. [ABSTRACT FROM AUTHOR]

Online monitoring for underground power cable insulation has become an urgent need in distribution grids, which can lead to proactive maintenance and avoid severe insulation faults. Insulation capacitance has been selected as an effective insulation condition indicator in many researches, but the variation of insulation conductance is always overlooked, resulting in a limited monitoring range and sensitivity. To solve this problem, a novel online monitoring method for underground power cable insulation based on resonance frequency analysis under chirp signal injection is proposed in this article. An online monitoring scheme based on common-mode chirp signal injection is first designed, realizing online monitoring in a nonintrusive manner. The resonance frequency under the injected signal is then analyzed, providing an effective approach to monitor insulation capacitance regardless of the accompanied insulation conductance variation. Simulations and experiments are carried out, proving the effectiveness of the proposed method for different system operating conditions. [ABSTRACT FROM AUTHOR]

Linear modulation techniques (LMTs) of an asymmetrical six-phase machine (ASPM) with two isolated neutral points synthesize the desired voltage vectors by applying at least five switching states. Different choices of applied voltage vectors, sequences in which they are used, distribution of dwell-times among the redundant switching states give rise to a large number of possible LMTs. It is desirable that these LMTs avoid more than two transitions of a particular inverter leg within a carrier period. Only a subset of existing LMTs of ASPM follows this rule. Through an innovative approach, this article finds a way to account for all possible infinitely many LMTs that follow the rule of at most two transitions per leg. Another important criterion for the selection of an LMT is its current-ripple performance. Therefore, through numerical optimization, this article finds optimal LMTs among the above infinite possible LMTs for all reference voltage vectors in the linear range and for the whole feasible range of a machine parameter. This parameter is related to the leakage inductance of the machine and impacts the current ripple performance of ASPM. An optimal hybrid strategy is proposed with these optimal techniques, which outperforms all existing techniques in terms of the current ripple. The theoretical analysis is validated through simulation in MATLAB and experiments performed up to 3.5 kW on a hardware prototype. [ABSTRACT FROM AUTHOR]

A new state-observer-based current balancing method for Modular Multilevel Converters with Interleaved half-bridge Sub-Modules (ISM-MMC) is presented in this article. The developed observer allows estimating currents through interleaved half-bridge legs in each submodule of ISM-MMC based only on arm current and submodule's capacitor voltage measurements. Then, the interleaved current balancing control uses the estimated currents to reduce the interleaved currents imbalance caused by upstream control actions. This technique minimizes the number of required current sensors in ISM-MMC, thereby reducing the converter's cost, weight, and volume. Capabilities of the proposed sensorless interleaved currents balancing control have been tested against standard parameter tolerances of the composing passive elements. In addition to that, a novel capacitor voltage balancing strategy for MMCs is developed. The new algorithm contains the main advantages of the classical sorting-based capacitor voltage balancing methods while providing an opportunity to decouple two balancing tasks of ISM-MMC, namely capacitor voltage and interleaved legs current balancing. The feasibility of the proposed methods is verified by extensive simulation and experimental tests on a laboratory prototype by the corresponding system response under the output characteristics variation and interleaved current control perturbation. [ABSTRACT FROM AUTHOR]

This article proposes a decoupled control scheme for the modular multilevel converter (MMC) to reduce the total harmonic distortion (THD) and eliminate one specific harmonic. First, to realize the decoupled control between the ac and dc paths of the MMC, an improved nearest level control (INLC) method is proposed. It applies the round function to generate the ac output voltage levels, instead of the arm output voltage levels. Thus, a staircase wave is generated by the INLC method. Then, by adding an additional pulse to each quarter of the staircase wave, one specific harmonic can be eliminated without optimizing each conduction angle. Furthermore, a decoupled circulating current fuzzy control method is proposed to suppress the second-order harmonic and balance the arm energy. By this decoupled control structure, the output voltage and the circulating current can be controlled independently. Taking the fifth-order harmonic as an example, simulation and experimental results validate that the proposed scheme can simultaneously realize THD reduction and one specific harmonic elimination in the MMC output voltage. [ABSTRACT FROM AUTHOR]

Cascaded split-source inverter (CSSI) is a single-stage modular multilevel structure. This article proposes the multidimensional pulsewidth modulation (MD-PWM) for this topology. All multilevel modulations are a particular version of this approach. The principles of this geometrical method are based on selecting the optimal points and determining the switching sequences and time intervals. By considering the operational principles of CSSI, this method is modified to accurately control the voltage of dc links, charge inductors with constant duty cycles, control dc and ac sides of cells independently, and reduce the reverse recovery effects of input diodes. MD-PWM, with a low computational burden, can be implemented for CSSI with any number of voltage levels. The output power can be distributed equally or unequally among cells, and both buck and boost operation modes are realized for each cell. Also, this method is extended for the operation of the converter with unequal input sources. For an asymmetric topology with N cells, harmonics are located at multiples of N times switching frequency. Thus, this strategy eliminates low-frequency distortions from the output voltage of asymmetric CSSI. The simulation and experimental results verify the performance and accuracy of the proposed technique and mathematical relations. [ABSTRACT FROM AUTHOR]

This article explores a single-source UXE-type asymmetrical multilevel inverter for its operation on 13-, 11-, and 9-levels with boosted output voltage. The 13- and 11-level operations require a single voltage sensor to maintain the auxiliary dc link at $V_{\text{dc}}/2$ and produce 1.5 and 1.25 boosting using redundant states and exhibit lower capacitor inrush currents. For the 9-level operation, the topology exhibits self-balancing of the dc-link at $V_{\text{dc}}$ and a boosting of 2. With a conventional pulsewidth modulation (PWM) for the 13-level operation, the inverter can drive a predominantly inductive load of 0.35 lagging at unity modulation index. For the 11-level operation, the levels cease to maintain beyond the modulation of 0.95. Thus, a hybrid PWM is proposed to fully utilize the redundant states for the charging of the switched-capacitors and enhance the inverter active load capability in the 13-level mode by 21% at unity modulation index ($m_a$) and address a 0.8 power factor load at the $m_a$ of 0.9. For the 11-level operation, the levels are maintained at any $m_a$ with the hybrid PWM. The operation of the inverter is also verified for nonlinear load. Further, the 9-level operation with twice boosting and self-balancing is presented. The results are verified on MATLAB/Simulink and validated experimentally. [ABSTRACT FROM AUTHOR]

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

Existing dc and ac bypass-assisted two-level three-φ inverter topologies can only reduce the peak-to-peak (P-to-P) common mode voltage (CMV) value by 66.6%. However, the dv/dt of CMV remains unchanged. This issue can be easily addressed by using a multilevel inverter but it increases the size, cost, and complexity of the system. As an alternative, this article proposes a novel three-phase inverter topology where one leg (out of three) of the inverter is configured to produce three-level pole voltage while the other two legs produce two-level pole voltages. This results in a unique space vector (SV) diagram with 12 SVs, whereas a 2-level inverter has only 8 SVs. A new pulsewidth modulation scheme is proposed that can utilize the SV diagram in such a way that dv/dt of CMV is reduced by 50% along with a 66.6% reduction in CMV P-to-P value in each switching cycle. Another advantage of the proposed topology is the reduced conduction losses due to fewer switches conducting at any given time. The proposed topology is compared with the existing solutions to prove its advantages. Simulation and experimental results are presented for a three-phase induction motor load to validate the various claims. [ABSTRACT FROM AUTHOR]

The two-level voltage source inverter fed dual three-phase motor (DTPM) induces the high-frequency common-mode voltage (CMV) and generates the unwanted adverse effects. As one of the effective common-mode suppression methods, the conventional CMV elimination (CMVE) pulsewidth modulation (PWM) schemes are generally based on the voltage-balance mode for DTPM systems which suffer from the parameter asymmetry induced phase current imbalance. This article proposes two current-balance mode unified CMVE PWM schemes which has no restriction on the reference voltages and angle displacement between the two sets of three-phase windings. Thus, the proposed methods can be utilized in different types of DTPMs with different angle displacements between the two winding sets, and the CMVE effect can be retained both in the conditions of symmetrical and asymmetrical system parameters which is more practical than conventional CMVE schemes in real application. The function and performance of the proposal is proved by simulations and experiments. [ABSTRACT FROM AUTHOR]

Four-switch buck-boost (FSBB) converter features positive output voltage and low voltage stress of power switches. In this article, a pulsewidth modulation plus phase-shift control scheme is proposed to achieve zero-voltage-switching for all the power switches in full input voltage and load range and minimize the inductor current ripple and root mean square (RMS) value. The implementation of the proposed control scheme is given. A prototype of a 500-W FSBB converter is built and tested in the lab, and the experimental results verify the effectiveness of the proposed control scheme. [ABSTRACT FROM AUTHOR]

This article proposes a novel pulsewidth modulation (PWM) modulation algorithm for multiphase conventional matrix converters, with three inputs and $k$ outputs, using the transfer function of the load angle. The proposed approach extends the range of power angle control at the input during the operation with a maximum voltage transfer ratio. The proposed concept is based on the direct analytic voltage PWM modulation with an elliptical trajectory of reference load voltages. The proposal has been verified using the circuit simulation in PSIM software, symbolic analysis using MATLAB, and finally through an experiment. [ABSTRACT FROM AUTHOR]

The stability of power electronic devices is prone to instability when supplying constant power loads (CPL) due to their negative impedance specifications. This necessitates an efficient control methodology to overcome the destabilization issue and regulate the response of the output voltage. In particular, this article proposes a novel interval type-III fuzzy neural network-based model predictive control (IT3FNNMPC) to mitigate the destructive effects of CPL in dc/dc boost converters implemented in the microgrid (MG) and power system distribution. In a typical MGs configuration, the IT3FNNMPC controller is formulated and designed in a constraint control problem to achieve a fast-transient response of system voltage. The feasibility and applicability of the designed IT3FNNMPC controller have been validated by hardware-in-the-loop real-time simulations. [ABSTRACT FROM AUTHOR]

High-performance comprehensive optimization of line current ripple, zero-sequence circulating current (ZSCC), and switching losses is a challenge for parallel interleaved inverters. This article proposes a modified discontinuous pulse width modulation (PWM) method for two parallel interleaved two-level voltage-source inverters (2L-VSIs), which are regarded as a single 3L-VSI to optimize its vector sequence. The line current ripple is the priority optimization target to guarantee the principle of the nearest three vectors is applied in each subsector. To reduce the ZSCC and switching losses, the vector combinations with smaller changing rate of ZSCC are selected, and the phase-leg carrying the highest current is clamped. The detailed design procedure of 3L-vector sequence and how to distribute to 2L-VSIs are revealed. The quantitative performance comparison between the proposed PWM method and existing ones in terms of line current ripple, ZSCC, and switching losses are made. Experimental results confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is widely used due to its various advantages. However, it causes serious electromagnetic interference (EMI) problems. Therefore, it is necessary to suppress the conducted EMI of MMC. A novel spread-spectrum (SS) strategy, called space SS (SSS), is proposed in this article. The core idea of the SSS strategy is to make the carrier frequency of each submodule different. The principle and formula derivation of the SSS strategy are elaborated. SSS is a highly free strategy because carrier frequency can be distributed arbitrarily with space position. Several methods for determining carrier frequency distribution are proposed in this article. These methods not only achieve EMI suppression, but also take into account less circulating current, higher switching frequency, and lower switching loss. Total harmonic distortion (THD) and switching loss variation under the SSS strategy are also studied in the article. Experiments are carried out to validate the effectiveness of the SSS strategy. The SSS strategy can reduce the EMI by more than 12 dB and all obvious spikes in the spectrum are eliminated effectively. Besides, it is easy to implement and suitable for practical systems with quantities of submodules. [ABSTRACT FROM AUTHOR]

In this article, a hybrid modular multilevel converter (MMC) topology is proposed, in which two of the submodules (SMs) are based on SiC mosfet, while others are based on Si IGBT. In the proposed hybrid topology, the capacitor voltage of SiC SM is controlled to be half of that of Si SM, which reduces the requirement for the blocking voltage of SiC mosfet. What is more, this article improves the modulation scheme to move most of the switching actions from Si SMs to the two SiC SMs, which strengthens the merits and avoids the shortcomings of SiC mosfet. Besides, to solve the voltage imbalance problem caused by the change of topology and modulation scheme, a specialized voltage balancing scheme is proposed. Finally, the simulation and experiment result proves the feasibility of the hybrid MMC and control scheme, and the comprehensive analysis verifies that the hybrid MMC can achieve a better balance among cost, loss, and feasibility compared with others. [ABSTRACT FROM AUTHOR]

A mathematical analysis of four-level (three-phase) phase-shifted carrier modulation class-D amplifiers with analog feedback is proposed. The nonlinear difference equations are extracted and solved using the perturbation theorem. In this way, a closed-form function describes the low-frequency part of the output for an arbitrary input signal. The results are generalized for an arbitrary number of levels by analogy, well matched with the previous model of two-, three-, and the proposed four-level ones. The analytical results confirm that, apart from switching frequency, the multilevel class-D amplifiers converge to linear amplifiers as the number of output levels increases. An analytical equation expresses the harmonic distortion of practically interesting five-level amplifiers with bridge-tied load. The model is verified by system-level simulations and circuit-level implementation. In this way, a prototype fully differential five-level circuit is implemented on the printed circuit board to confirm the model. [ABSTRACT FROM AUTHOR]

The realization of zero voltage switching (ZVS) of the bidirectional inductive power transfer (BIPT) system is critical to system stability and transmission efficiency. For the symmetrical phase shift modulation (SPSM) strategy, as system transmission power decreases, it is necessary to reduce the phase shift angle of the fundamental component of ac excitation voltages on both sides to achieve ZVS. However, it will result in a decrease in the system transmission power factor and transmission efficiency. In this article, an asymmetrical pulsewidth modulation with even harmonics (APWMEH) strategy is proposed for the BIPT system to optimize the transmission efficiency under light load conditions. First, this article analyses the relationship between ZVS and transmission efficiency of the BIPT system with SPSM. Second, the APWMEH control technique is proposed, including the analysis of the working modes of both full bridges, the condition of the ZVS realization, and the efficiency optimization of the system. Then, the control scheme of power regulation and load matching of the system are given. Finally, the comparative analysis and experimental results are performed at a BIPT experimental platform. Compared with symmetrical triple phase shift and fundamental dual phase shift, the transmission efficiency of the BIPT system with AWMEH is improved significantly under the light load conditions. [ABSTRACT FROM AUTHOR]

Cascaded split-source inverter (CSSI) is a new single-stage modular multilevel topology. Each cell of this converter converts dc to ac power in the buck or boost operation mode without any additional power switch. This article develops a design method based on a detailed model for CSSI. This model shows that energy storage elements experience double-fundamental frequency ripples besides high-frequency ones. It accurately calculates voltage gains and capacitor voltage and inductor current ripples. On the other hand, common carrier-based multilevel modulations have been modified in terms of both reference and carrier signals to control the inverter under symmetric and asymmetric conditions. With proposed simple modulations, the cell inductor is charged with the constant duty cycle. Also, the reverse recovery of diodes occurs in the minimum level of input current once per switching cycle and output power is distributed equally between cells. These characteristics reduce power losses, the input inductance of each cell, and the complexity of the system model. By phase-shifted pulsewidth modulation (PWM), the output voltage harmonics of three-cell CSSI are centralized around multiples of the triple switching frequency. In this method, high-frequency ripples on the network impedance are one-third of those in level-shifted PWM. Also, CSSI has been compared with cascaded multilevel inverters with voltage boosting ability and other SSI-based multilevel topologies. Validity of operation principles, mathematical relations, and modulation schemes are verified through simulation and experimental results. [ABSTRACT FROM AUTHOR]

Non-isolated high-gain dc–dc converters are essential for applications with low input voltage, such as solar PV modules and fuel-cells. Due to the high step-up conversion ratio, the input current increases significantly with increase in power rating. This leads to considerable conduction loss in the non-ideal elements of the converter, degrading the efficiency. Moreover, peak-to-peak ripple of the input current also increases with an increase in power rating. This increases the size of the passive elements, thereby limiting the power density. An n-phase Interleaved Complementary Current-fed Topology (n-phase ICCFT) is proposed in this article to address the aforementioned limitations. Two pulse width modulated (PWM) schemes are proposed to implement the interleaving of the n-phases. Detailed steady-state analysis with various operating modes and the gain characteristics of the proposed converter are analyzed in the article. A comparative analysis of the two PWM schemes in terms of ripple characteristics, capacitor current stress, and power loss is reported. Operation of a two-phase ICCFT with the proposed PWM schemes is verified using PLECS simulation and experiments using a proof-of-concept hardware. [ABSTRACT FROM AUTHOR]

Series-cascaded microgrids (MGs) are gaining increasing popularity because of their control flexibility and ability to synthesize high voltage levels from low power rated modules. Several control schemes have been reported for autonomous power sharing in series-cascaded MGs that incorporate dispatchable distributed generators (DGs) only. In contrast, this article develops a series-cascaded MG formed by dispatchable and nondispatchable DGs. Achieving power balance as well as voltage and frequency regulation in this MG configuration is a challenging task. In this article, we propose a decentralized master–slave control scheme that regulates voltage and frequency and maintains power balance. The proposed scheme ensures the maximum utilization of nondispatchables, incorporates autonomous power curtailment under light-load conditions, and offers system reliability comparable with the traditional parallel structure. The proposed MG configuration and control scheme are thoroughly validated via simulations and experiments under various operating scenarios. [ABSTRACT FROM AUTHOR]

This article presents a fast direct pulsewidth modulation (PWM) algorithm for the conventional matrix converters developed in Verilog hardware description language. All PWM duty cycle calculations are performed in one cycle by an atomic operation designed as a digital module using field-programmable gate array basic blocks. The algorithm can be extended to any number of output phases. The improved version of the discontinuous direct analytic voltage PWM (DAV-PWM) method is proposed, in which the use of trigonometry, angles, and program loops has been eliminated. The proposed DAV-PWM is equivalent to the space vector modulation; it can be applied during input asymmetry and also allows for the control of the displacement input angle. The proposal has been verified using the circuit simulation in PSIM, digital structure modeling in ModelSim, and finally through an experiment. [ABSTRACT FROM AUTHOR]

Generating multiple voltage levels requires a number of capacitors in a flying capacitor (FC) inverter, which is of crucial importance to the cost and power density of the whole system. Often the flying capacitance requirement is a tradeoff between accepted voltage ripple peak-to-peak value and the switching frequency of the inverter. Based on the popular phase-shifted pulsewidth modulation (PSPWM), the peak-to-peak value of the FC voltage ripple is first derived as a function of operating conditions in the time-domain. Since it is not an optimized way to simply adjust the flying capacitance for making the voltage ripple meet the requirement under constant switching frequency of the inverter, a variable switching frequency PSPWM (VSF-PSPWM) for FC voltage ripple control is presented in this article. From the point of view of FCs, the proposed VSF-PSPWM can satisfy the same requirement of the voltage ripple peak-to-peak value with a lower switching frequency and hence reduce the switching losses, comparing with the normal constant switching frequency PSPWM (CSF-PSPWM). Due to the real-time variation of switching frequency, the proposed VSF-PSPWM demonstrates the advantage in electromagnetic interference peak reduction. The simulation and experimental results are presented to evaluate the performance of the proposed method against the traditional CSF-PSPWM. [ABSTRACT FROM AUTHOR]

Multilevel inverters are becoming more and more popular in photovoltaic applications because of lower total harmonic distortion, lower switching stress and lower electromagnetic interference. In this article, a single-phase five-level transformer-less PV inverter is proposed for the purpose of leakage current reduction. The inverter is based on a flying capacitor (FC) configuration, the voltages of FCs are balanced at Vdc/4 through the coordination of the two half-bridge at the switching frequency, helps to reduce investment cost in passive elements. Two bidirectional circuits are added to guarantee a constant common-mode (CM) voltage. The leakage current elimination mechanism is analyzed in detail with operational states and CM equivalent model. The losses are analyzed, the control strategy and the FCs are detailed designed. A comparison is also made in terms of the number of elements, voltage stress and CM voltage. Experiment results under grid-connected condition show that the proposed topology achieves both excellent differential-mode and CM performance. [ABSTRACT FROM AUTHOR]

In this article, we propose steady-state modeling of dc–dc converters driven by multiple pulsewidth modulation (PWM) signals. The proposed dc–dc converter modeling uses a switched state-space framework, and the switching signal discontinuities are represented by a Fourier series to obtain the average model. The advantage of the proposed modeling is that it is not dependent on the dc–dc converter topology, and the dimension of the state-space model does not increase with the number of storage devices. Additionally, the duty cycle and phase displacements among the driving PWM signals can be arbitrary and systematically modeled. The effectiveness of the proposed modeling is supported by simulation and experimental results. [ABSTRACT FROM AUTHOR]

The diode-front-end (DFE) cascaded H-bridge (CHB) inverter has prevailed in the nonregenerative industry drive domain for high power medium voltage applications due to its modularity, scalability, and fault-tolerant capability. The regenerative version of the CHB drives is made possible by adding the extra active-front-end (AFE) rectifier in each power cell, such as a three-phase Pulse width modulation (PWM) rectifier. However, AFE introduces the switching harmonics which requires to be attenuated by designing a grid interfaced filter to comply with the harmonic standard IEEE 519-2014. High-order filters like LCL filters are not preferred due to complex inherent resonances in a multiparallel AFE system. A large number of capacitive components in the system rouse multiple resonances, which decreases system reliability and modularity. This article proposes an active filtering strategy based on the optimal asymmetric carrier-shifting method for regenerative CHB drives with only L filters. The required filter size is reduced significantly while complying with IEEE 519-2014 standard and thus improves the overall size, cost, and efficiency. The proposed filtering strategy is validated experimentally using a seven-level regenerative CHB drive. [ABSTRACT FROM AUTHOR]

This article studies the model predictive control (MPC) for a twisted buck–boost inverter based on unfolding circuit. The focus is on the practical implementation of the MPC algorithm for the microcontroller designed for application in power electronics. Selection of proper cost function parameters along with a continuous control set reduced prediction horizon, at the same time keeping good quality of the grid current. The results showed that simplified differential equations and a multicore microcontroller contribute to the sample time reduction, which in turn increases the sampling frequency with the corresponding increase in the output current quality. The simulation and experimental results confirmed theoretical predictions. In conclusion, the MPC technique suits for reducing zero-crossing distortion and in applications based on unfolding circuit. [ABSTRACT FROM AUTHOR]

Five-phase induction machines are attractive due to inherent benefits such as lower current rating than three-phase ones. On the other hand, ac motor drives often need to operate in the overmodulation (OVM) region, e.g., to increase the maximum speed or to work with reduced dc-link voltage. Most of the existing OVM strategies for five-phase drives are based on injecting low-order harmonics in the no-torque xy plane while avoiding low-order α−β harmonics (at least up to a modulation index of 1.2311 p.u.), so as to prevent the torque ripple associated with the α−β components. However, in practice the x−y impedance is very small, and hence, this approach can easily lead to overcurrent. This article proposes an OVM method for five-phase induction motors that adaptively modifies the injected components so that at each moment the addition of low-order x−y harmonics is favored over α−β ones but without surpassing the maximum current rms of the drive. In case the total stator copper loss (SCL) tends to exceed its rating during OVM in a given scenario, the proposed scheme automatically reduces the x−y injection to keep the SCL at its rated value. Experimental results verify the theory. [ABSTRACT FROM AUTHOR]

Leakage current issues are worthy of attention for nonisolated grid-connected systems. This article introduces the method of eliminating common-mode (CM) voltage and reducing the leakage current based on modulation, and analyzes the correlation between actual effects of the method and the flying capacitor (FC) voltage balance in three-phase three-level FC grid-connected inverter. The proposed carrier-based modulation can balance the FC voltage by changing the transmission sequences of pulses and theoretically achieve zero CM voltage. In order to deal with the low frequency fluctuation and bias voltage of FC caused by asymmetry of actual hardware, the control method is introduced, which controls FC voltage by changing the action times’ distribution of switches, while still eliminating the CM voltage. Simulation and experimental results are provided to validate that the proposed method can control FC voltage and achieve good performance in suppressions of CM voltage, leakage, current and CM electromagnetic interference noise. [ABSTRACT FROM AUTHOR]

Beat phenomenon is an important issue for the practical application of electrolytic capacitorless motor drives. In this study, the characteristics of stator current harmonics caused by the voltage sampling delay are analyzed. Further, the beat phenomenon generated from the interaction between the harmonics and the fundamental currents is investigated, and the envelope feature of the stator current is derived mathematically. For the purpose of suppressing the beat phenomenon, a voltage reconstruction strategy is proposed to reduce the influence of dc-link voltage sampling delay at the six times of grid frequency. By utilizing the reconstructed dc-link voltage for calculation of PWM duty ratio, the beat phenomenon can be attenuated significantly. The proposed method can be integrated into motor control system easily. Experimental results show the effectiveness of the proposed strategy in a prototype of electrolytic capacitorless permanent magnet synchronous motor drive. [ABSTRACT FROM AUTHOR]

This article proposes a dual-inverter pulsewidth modulation (PWM) scheme for dc-biased vernier reluctance machines (dc-biased-VRMs) with reduced switching frequency capable of zero-sequence current regulation. The dc-biased-VRM utilizes the additional dc bias current in armature winding to construct the rotor flux. To regulate the dc bias current, two sets of three-phase inverters with common dc bus are used to provide dc current flow path. In each switching cycle, the number of switching actions is doubled compared with the conventional three-phase inverter. There is still a certain optimization space for adjusting the dc bias current and reducing the switching loss. The proposed scheme reconfigures the zero voltage vector based on the discontinuous PWM (DPWM) scheme, it effectively reduces the switching actions, thus reducing the switching frequency and ensuring the low switching loss of the inverter. In addition, an inserted zero voltage vector regulation method is associated with the proposed DPWM scheme, and it assures the zero-sequence current regulation ability. Besides, by adopting complementary zero voltage vector distribution in odd and even sectors, the balanced voltage stress of upper and lower switching devices in each bridge arm is realized. The proposed dual-inverter PWM scheme does not require any additional devices, and it provides an effective solution to improve the efficiency of the dc-biased-VRM drive system. Finally, the effectiveness of the proposed scheme is verified experimentally. [ABSTRACT FROM AUTHOR]

A dual-dc output three-phase three-level ac–dc converter is proposed for low-frequency pulsed power decoupling applications. One of the dc output is connected to the dc pulsed load, whereas the other one is used as power decoupling port and connected to the decoupling capacitor. The voltage of the power decoupling dc port can vary in a wide range to reduce the value and volume of the power decoupling capacitor. A buck/boost converter is employed to interface the power decoupling port with the dc pulsed load. A modified space vector pulsewidth modulation strategy is proposed for the ac–dc converter, based on which independent voltage and power regulation of the two dc outputs is achieved. The steady-state power is directly fed to the dc load with single power conversion stage, and the low frequency pulse power is fed to the power decoupling port. As a result, high-power quality and efficient power decoupling with reduced power conversion stages are achieved. Operation principles, modulation, and control strategies of the ac–dc converter are analyzed in detail. A prototype is built and tested to verify the effectiveness and feasibility of the proposed ac–dc converter for pulsed load. [ABSTRACT FROM AUTHOR]

The series connection of a standard three-level active neutral-point-clamped (ANPC) inverter and two cascaded H-bridge (CHB) modules comprising the flying capacitors (FCs) instead of the isolated dc voltage sources forms a seven-level hybrid topology that is referred to as improved ANPC (I-ANPC) converter. This article proposes an active voltage balancing technique for control of this hybrid multilevel inverter. The suggested method is based on a set of effortless logic equations that aim to stabilize the FC voltages within the CHB modules at their requisite reference values as well as to control the output voltage of the overall hybrid converter based on the phase-shifted-carrier pulsewidth modulation strategy. The experimental results obtained from a single-phase I-ANPC inverter's prototype are presented to validate the proposed control technique and its simple logic equations. [ABSTRACT FROM AUTHOR]

An integrated boost-LC-resonant-flyback multimode converter with a wide voltage gain is proposed in this article. With three different pulsewidth modulation strategies, the proposed converter can realize three modes including high-, medium- and low-voltage-gain (LG), by multiplexing inductors and power switches. In the high-voltage-gain mode, it has better load characteristics than the conventional LLC converter through an extra energy storage stage. In the medium-voltage-gain mode, the working condition is similar to that of the conventional LLC converter, but the issues of current reflow and circulation can be addressed than reducing the conduction loss. In the LG mode, the proposed converter works as a flyback converter, and it has a higher conversion efficiency and simpler operation state than the conventional LLC converter. Additionally, all power switches can realize zero-current switching over a wide load range. The operating principle, voltage gain, design methodology, and control scheme are fully presented in this article. Finally, a laboratory prototype with 110 V input voltage, 0–5 A output current, and 24–165 V output voltage was conducted and verified the proposed solution. [ABSTRACT FROM AUTHOR]

This article improves the sensorless brushless dc (BLdc) motor drives using the pulse amplitude modulation (PAM) with dc current sensing. Comparing to conventional BLdc drives using pulsewidth modulation (PWM), PAM BLdc drives result in better drive efficiency especially at low speed. However due to six-step commutation, additional position detection issues are resultant for the sensorless operation. They consist of voltage spike at low speed and commutation delay at high speed. In this article, these BLdc position detection issues are improved based on the proposed continuous position estimation. At low speed, the commutation compensation with dc current sensing is developed to minimize the influence of voltage spike. At high speed, several voltage compensation schemes are applied to improve the commutation delay and maximizing high-speed operation region. A 320-W permanent magnet motor prototype is used for the experimental verification of proposed PAM BLdc drive. Comparing to the conventional BLdc drives, the PAM drive with proposed position estimation demonstrates the improvement on both low-speed dynamic response and high-speed steady state stability. [ABSTRACT FROM AUTHOR]

In this article, we develop a novel multiobjective controller to regulate the power converters of a class of dc microgrids connected to nonlinear constant power loads and linear resistive loads. The suggested control approach uses the nondominating sorting binary genetic algorithm (NSBGA-II) to directly design the on/off switching signal of the converters without using the pulsewidth modulation technique. The multiobjective controller minimizes the tracking error of the dc bus voltage and at the same time tries to reduce the total number of switching actions. Thereby, the developed controller tracks the desired reference with a reduced converter switching action and power loss by using a proper Pareto solution. Moreover, by employing the NSBGA-II algorithm, it is feasible to involve the switching frequency in the design procedure to enhance the performance. Exploiting the binary genetic algorithm instead of the conventional genetic algorithm (GA) turns a continuous surface searching into a binary one, which not only makes it more compatible with the nature of the power converter control but also decreases the online computational burden. To illustrate the superiority of the proposed approach, real-time OPAL results are provided. [ABSTRACT FROM AUTHOR]

In this article, we propose a novel switching-table-based direct torque control (ST-DTC) method to eliminate the current harmonics in dual-three-phase permanent-magnet synchronous machines due to the back electromotive force (back EMF) harmonics and voltage vector selection. By employing a novel space voltage vector selection strategy and the optimal action time for different groups of vectors, a novel ST-DTC method is developed. Furthermore, in order to implement standard pulsewidth modulation (PWM) switching sequence, a centralization PWM method for 36 voltage vectors is introduced. The proposed method can effectively reduce the phase current harmonics caused by both back EMF distortion and voltage vector selection, and still reserve the advantages of the conventional ST-DTC, such as fast torque response and simple structure. Its effectiveness is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

An isolated soft-switching dc–dc converter based on the t-type commutation cell and employing capacitive output filter is introduced in this article. A hybrid switching strategy is proposed, allowing the circuit to operate with a three- or four-level scheme relying on a unique duty cycle definition. The energy transfer process regarding two distinct continuous conduction modes is detailed and a complete static model is derived. Also, the requirements for the occurrence of zero voltage switching (ZVS) on the switches are evaluated, and a small-signal analysis is carried out to provide information on the dynamic behavior of the proposed circuit. The operation of the proposed converter is verified for the conditions of fixed input and output voltage and of wide input voltage range designs. Laboratory tests with a 1.2 kW prototype operating in closed-loop demonstrate the feasibility of the proposed circuit and validate the theoretical analysis carried out. [ABSTRACT FROM AUTHOR]

Interleaving is widely used in paralleled converters to enhance the output current quality, but subsequent circulating currents could lead to harmonic distortion and extra power losses. This article proposes an improved interleaved discontinuous pulsewidth modulation (IIDPWM) method to reduce zero-sequence circulating currents (ZSCC) in paralleled converters with common dc and ac bus. For two-paralleled converters, optimal vector sequences are selected considering minimal common-mode voltage (CMV) differences, the NTVs principle, and power losses. Furthermore, a novel carrier-based scheme is presented to implement the proposed strategy in a general case with any number of paralleled units. The 180 ° carrier phase shift between two unclamped phase legs in discontinuous PWM is first applied for ZSCC reduction. Compared to existing works, the proposed strategy shows a practical value achieving good overall performance in ZSCC, output currents, switching losses, ease of use and scalability. Simulation and experimental results verified the effectiveness of the proposed IIDPWM strategy. [ABSTRACT FROM AUTHOR]

A model predictive control (MPC) strategy based on optimal switching sequence concepts is presented for direct power control of grid-connected three-level neutral-point clamped converters. The proposed control strategy explicitly considers the modulator in its formulation along with the model of the system. Through two well-formulated optimal control problems, the proposed strategy is shown to optimally achieve control of the average trajectory of the active and reactive powers as well as the dc-link capacitor voltages without using weighting factors to tradeoff both control targets. Experimental results demonstrate this strategy produces improved steady-state performance with a well-defined output voltage spectrum and fixed-switching frequency while maintaining the inherent fast dynamic responses of MPC strategies. [ABSTRACT FROM AUTHOR]

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. [ABSTRACT FROM AUTHOR]

The modulation law of the two-level five-phase voltage source inverters is modelled with two decoupled subspaces and their respective reference voltages. A new voltage-time system based on the duty cycles for this topology is presented in this article. Then, an alternative scheme to the space vector modulation is developed by deriving an analytic solution for the case of study, which is achieved with a low-computational cost algorithm. The strategy reckons the duty periods of the power switches immediately and can be implemented straightforwardly in a digital controller. The zero-sequence voltage is also considered to provide multifrequency operation either in continuous or discontinuous switching modes. The experimental validation, considering the time and frequency responses, supports the theoretical derivations in the introduction of this new method. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have offered significant contributions toward the implementation of energy conversion units used in industry and renewable energy applications. However, the switching devices in MLIs are associated with power loss division problems. The pulsewidth modulation (PWM) techniques greatly influence the peak, average, and ripple values of the device junction temperature. Thermal tension in the devices may be raised due to increased power loss caused by additional switching or uneven distribution of losses due to unbalanced gate pulses. Higher thermal stress accelerates the life degradation process of the power devices, and, eventually, leads to permanent damage of the MLI. Therefore, a new loss balancing two-pole clamped PWM technique for a single-phase MLI is proposed in this article. In the proposed PWM technique, in each half line cycle, symmetrical and equal duration of nonswitching zone is placed on the two reference signals alternately. Due to symmetrical and equal duration of clamping action, the unbalanced gate pulses become balanced after each half line cycle. The proposed technique extends the reliability of the power devices by improving the loss division performance and the junction temperature characteristics. Moreover, the reduction of neutral point potential swing reduces the output total harmonic distortion. The improved performance of the proposed technique is validated by simulation in MATLAB/Simulink and experimental results from downscale laboratory prototype test platform. [ABSTRACT FROM AUTHOR]