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In this paper, a fixed-switching-frequency closed-loop modulation of a voltage-source inverter (VSI), upon the digital implementation of the modulation process, is analyzed and characterized. The sampling frequency of the digital processor is considered as an integer multiple of the modulation switching frequency. An expression for the determination of the modulation design parameter is developed for smooth modulation at a fixed switching frequency. The variation of the sampling frequency, switching frequency, and modulation index has been analyzed for the determination of the switching condition under closed loop. It is shown that the switching condition determined based on the continuous-time analysis of the closed-loop modulation will ensure smooth modulation upon the digital implementation of the modulation process. However, the stability properties need to be tested prior to digital implementation as they get deteriorated at smaller sampling frequencies. The closed-loop modulation index needs to be considered maximum while determining the design parameters for smooth modulation. In particular, a detailed analysis has been carried out by varying the control gain in the sliding-mode control of a two-level VSI. The proposed analysis of the closed-loop modulation of the VSI has been verified for the operation of a distribution static compensator. The theoretical results are validated experimentally on both single- and three-phase systems. Index Terms--Closed-loop modulation, distribution static compensator (DSTATCOM), field-programmable gate array (FPGA), multisampled, switching condition.

In this paper, the method of triangular carrier switching control of two-level inverters is extended to cascaded multilevel inverters using phase-shifted multicarrier unipolar pulsewidth modulation (PWM). The condition for smooth modulation is obtained using the Bessel's function representation of the PWM output and the switching condition of the multilevel-inverter-controlled system. A method is proposed for the determination of the minimum amplitude of the triangular carrier for smooth modulation at fixed switching frequency. It is shown that the multilevel modulation based on the phase-shifted carriers significantly reduces the ripple magnitude in the switching function and allows the use of a smaller carrier amplitude under closed loop. This increases the forward gain and, hence, improves the tracking characteristics. The proposed cascaded multilevel inverter control is implemented for the operation of a distribution static compensator (DSTATCOM) in the voltage control mode. The experimental verification of the theoretical and simulation results is provided through a field-programmable gate array (FPGA) based control of a laboratory model of a single-phase DSTATCOM. Index Terms--Bessel's function, carrier amplitude, cascaded multilevel inverter, distribution static compensator (DSTATCOM), field-programmable gate array (FPGA), multilevel modulation, switching control.

Nonisolated dc–dc converters are fundamental building blocks in the power supply for a wide range of applications. To cater to this heterogeneity in applications, development of dc–dc converters with suitable voltage conversion ratio (G) is imperative. Given a converter topology, G can be found out uniquely by using the principle of inductor volt-second balance, and the process of obtaining the voltage conversion ratio from the topology is simple. In contrast, the inverse problem, i.e., the process of obtaining the converter topology for a given voltage conversion ratio (G) is a challenging task, and the obtained topology is also not unique. This article presents a simple method to obtain a family of converter topologies from a required voltage conversion ratio. This method utilizes the principle of inductor flux balance as a synthesis tool. The step-by-step procedure to synthesize the converter topologies is outlined. To illustrate the efficacy of the proposed method, it is applied to synthesize various quadratic buck–boost topologies, and a family of converters is identified. Operation and feasibility of two novel topologies, identified by the proposed theory, are verified experimentally. [ABSTRACT FROM AUTHOR]

Due to the pulsating power at the inverter output terminals, the passive storage elements of the boost stage of the current-fed switched inverter (CFSI) contain a power frequency harmonic component (100 Hz), apart from dc and switching frequency components. In prior designs, the second harmonic component is suppressed by increasing the size of the input filter inductor and capacitor or by using additional circuits. This paper presents a complete characterization of a control-based approach to suppress the power frequency harmonic component in the input inductor current of a CFSI. It also presents a comprehensive characterization of the harmonic power redistribution. Using the proposed approach, it is demonstrated that the inductor value of a CFSI is reduced by 61% for the same peak-to-peak ripple. This leads to an improvement in the conversion ratio, efficiency, and power density of the overall converter. A SiC MOSFET-based CFSI with 75-kHz switching frequency is used to verify the proposed design philosophy. [ABSTRACT FROM AUTHOR]

Power-hardware-in-the-loop (PHIL) simulations are used to test power hardware with the help of computer-based real-time simulations. Generally, buck-based power amplifiers that have good dynamic performance are used to construct a PHIL simulator because of their linear large signal control-to-output characteristics. However, their output voltage peak is limited to the applied dc input in the linear region of modulation. In this paper, a differential boost converter (DBC)-based power amplifier is proposed for PHIL simulations, which does not suffer from the aforementioned limitations of a buck-based amplifier. A conventional DBC exhibits highly nonlinear control-to-output behavior. A feedback linearization technique is used to linearize the DBC in a large signal and dynamic sense, which makes it suitable for PHIL applications. Using this power amplifier and a MATLAB/Simulink toolbox for real-time simulations, the PHIL simulator is constructed. Experimental results under various operating conditions of source voltages, such as unipolar, bipolar, transients in frequency, and the dc step, and various load conditions, such as reactive, nonlinear, and transient faults, are provided to confirm the efficacy of the proposed PHIL simulator. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Electronic load (E-load) is commonly used to test power supplies. In order to test computer power supplies, the E-load must possess an ideal controlled current source property which draws a desired load current even in the case of a very low terminal voltage of the source under test (SUT). It also needs to have superior dynamic performance to simulate high-slew-rate load transients. This paper proposes the design of a switching-converter-based E-load with very large operational bandwidth. The overall architecture of the E-load consists of a low-bandwidth converter, which functions under steady state, and a high-bandwidth auxiliary circuit that is only active during transient state. The converter circuit is realized using a novel switched-boost topology, and the auxiliary circuit is realized using a MOSFET operating at the edge of saturation and linear region. The proposed topology is capable of sinking a specific amount of load current even with a very low SUT terminal voltage. Simulation and experimental validations are provided to verify the proposed concepts. A prototype has been built to test the proposed architecture. The operational input voltage (SUT voltage) ranges of the prototype are between 0.5 and 6 V. The load current range is between 0.75 and 7 A. The results validate the excellent dynamic characteristics of the proposed architecture. [ABSTRACT FROM PUBLISHER]

In this paper, a generalized multiband hysteresis modulation and its characterization have been proposed for the sliding-mode control of cascaded H-bridge multilevel-inverter (CHBMLI)-controlled systems. A frequency-domain method is proposed for the determination of net hysteresis bandwidth for a given desired maximum switching frequency of the inverter. The switching transition concept of Tsypkin's method and the describing function of nonlinear relay have been used for the derivation of results. A hierarchical switching algorithm has been suggested for the modular cells of the cascaded multilevel inverter. The hierarchy of each cell is swapped sequentially to provide the self-balancing capability in case the dc-link voltage is supported by the capacitors. The simulation and experimental verification of the derived results are provided through a single-phase distribution static compensator (DSTATCOM) model. The application in the three-phase system has been shown through simulation studies on a 3.3-kV distribution-system compensation using DSTATCOM. Verification on both single- and three-phase systems is obtained using a five-level cascaded-multilevel-inverter topology. [ABSTRACT FROM AUTHOR]

This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three-and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations. [ABSTRACT FROM AUTHOR]