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In this paper, a single-inductor dual-output (SIDO) dc–dc converter is proposed. The significant feature of the proposed converter is feeding a constant power load in low-voltage side (LVS) port, where even feeding a variable load at LVS does not have any cross regulation to high-voltage side port with the desired approximation. Magnificently, both merits are obtained in open-loop manner, which is an outstanding characteristic in comparison with that of the existed converters. In this paper, soft commutation and soft switching of switches and diodes are investigated along with the aforementioned main novelty. Moreover, detailed theoretical analyses of the proposed SIDO dc–dc converter in continuous conduction mode are presented besides the comparisons with some other structures. Finally, theoretical analyses are verified through a 1500 W experimental prototype results. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes two coupled-inductors-based Z-source networks, called the modified series and tapped switched-coupled-inductors quasi-Z-source networks (mSSCL-qZSN and mTSCL-qZSN, respectively). These networks offer high voltage gains with less-than-unity winding turn ratios $(n < {\text{1)}}$ , resulting in a reduced inductive element size. Other advantages include a less number of active components and their lower ratings and a higher efficiency. In addition, a lower magnetic core size is required for the proposed ZSNs due to the lower peak magnetizing current. The performance principles and detailed comparative analysis are provided and confirmed through experiments on a 200-W dc–dc converter. [ABSTRACT FROM AUTHOR]

In recent years, modular multilevel converter (MMC) is considered for medium-voltage variable speed drives (VSD) due to its modularity and higher reliability. However, the major drawback of the MMC-based VSD is the higher capacitor ripple voltage at lower operating speeds. In literature, this ripple voltage is reduced by injecting a high-frequency circulating current into each arm. This additional circulating current increases the overall current rating of the devices, inductors, and capacitors. Alternatively, the capacitor ripple voltage can be reduced at the lower output frequency by reducing the dc-bus voltage. This paper proposes a new configuration using a multipulse diode-bridge rectifier to reduce the dc-bus voltage when the drive is operated at lower speeds. Therefore, the capacitor ripple voltage decreases without injecting any circulating current. In addition, a new technique is proposed to maintain the peak-to-peak value of the submodule capacitor ripple voltage constant at near-zero speed. The proposed converter with 24-pulse rectifier configuration is simulated in MATLAB/Simulink, and the experimental validation is carried out on a prototype with 12-pulse rectifier. [ABSTRACT FROM AUTHOR]

In this paper, a novel transformerless interleaved high step-down conversion ratio dc–dc converter with low switch voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive voltage division, the main objectives of the new voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses of active switches. As a result, the proposed converter topology possesses the low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input voltage, 25-V output voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance. [ABSTRACT FROM PUBLISHER]

Direct current voltages unbalance of respective power cells is an inherent and critical problem in a cascaded multilevel converter, which is widely used in the solid-state transformer. In this paper, an n -dimension space vector pulse width modulation is presented to address this issue in a three-level H-bridge-based cascaded multilevel converter. This algorithm utilizes the redundant switching pairs of the inner cell and the redundant vectors of mutual cells to balance capacitors’ and cells’ voltages. Meanwhile, a smooth vector transition strategy is included in this algorithm to avoid the level-skip phenomenon. The calculation processes are analyzed in one-cell, two-cells, and three-cells modes, respectively. It is simple, calculable, and flexible to extend in n-cells mode. Finally, the voltage balancing capacity of the inner cell and mutual cells with smooth level transition are verified by simulations and experiments not only at startup but also with unbalanced loads. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper proposes an interleaved-stage ac–dc bidirectional power converter topology feasible to medium-voltage railway systems. It is based on an arrangement that uses input-series-output-parallel configuration with identical power modules. Each module consists of two interleaved legs employing coupled windings so that it is possible to connect a medium-frequency transformer. The topology conception is presented, followed by the adopted control and modulation technique. An estimation of semiconductor losses is also discussed, while a comparative analysis by means of simulation results validates the improved performance of the introduced approach if compared with similar solutions. The topology results are obtainedt through a medium-voltage high-power railway application, demonstrating the converter functionalities and performance under both steady-state and dynamic conditions. It is then possible to state that good performance in terms of efficiency is achieved even though the power stage presents higher component count if compared with the topology that presents the best result, thus making it suitable to high-power ac–dc machine drive applications. [ABSTRACT FROM AUTHOR]

In this paper, a power factor correction (PFC)-based switched reluctance motor (SRM) drive is proposed. Generally, the SRM drive is fed with a simple diode bridge rectifier followed by a bulky capacitor, which draws peaky current at low power factor and high-input-current total harmonic distortion (THD). Here, a dual output converter is proposed to control the SRM and to provide power quality improvement as well. This converter is a combination of Cuk and SEPIC converters, which produces two equal output voltages with neutral point N, to feed a midpoint converter of the SRM drive. The converter is designed to operate in discontinuous conduction mode of operation to obtain inherent PFC at supply side. The motor control is attained by regulating dc link voltage over a wide range. Test results on a prototype of the SRM drive demonstrate the excellent performance with high power factor and reduced input current THD. The observed power quality indices depict the improved power quality as per the standard IEC 61000-3-2. [ABSTRACT FROM PUBLISHER]

In this paper, a new type of matrix converter (MC) also called a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed. The proposed converter can provide step-down operation of the input voltage with various types of output voltages such as in-phase and out-of-phase output voltages, rectified (or positive) output voltage, and output voltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saves an extra bulky line frequency transformer, which is required for the conventional MCs to provide electrical isolation and safety, when used in application such as dynamic voltage restorers, etc. Two different circuit variations of the proposed HFTI MC are presented with and without continuous output currents, with the latter having less passive components. The safe-commutation strategy is also employed for the proposed HFTI MC to provide current path for the inductor during dead-time, which avoids switch voltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also developed to obtain various output voltages. Moreover, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output voltages, and output voltage with step-changed frequency. [ABSTRACT FROM PUBLISHER]

This paper presents a new formulation of a finite control set model-predictive control (FCS-MPC) algorithm, allowing to determine the best commutation instant in order to optimize the converter current tracking. This algorithm, mixing properties of FCS-MPC method and time resolution related to pulse width modulation schemes, is illustrated in a parallel flying capacitor converter. The parallel association of classical commutation cells is a good solution for increasing the output current driven by the converters, while the standard semiconductor technology is used. The control strategy used with this type of connection must be able to ensure not only a good distribution of the output current among the different legs, but also the balancing of the floating capacitor voltages. [ABSTRACT FROM PUBLISHER]

Phase-shifted carrier modulation is an industry standard in its application to multilevel H-bridge converters. The major advantage of this scheme over level-shifted and space vector modulation schemes is its inherent ability to evenly distribute losses between semiconductor devices. However, phase-shifted schemes suffer from harmonic degradation when operated at the low carrier frequencies required in high-power high-level number applications. This paper develops a model predictive modulation (MPM) scheme that achieves superior harmonic performance, compared to phase-shifted modulation, while ensuring equal semiconductor loss distribution. With respect to complete-enumeration-based predictive techniques, the proposed modulation significantly reduces the number of times the system cost function is evaluated. Reducing the number of calculations by several orders of magnitude ensures computational feasibility. Simulation and experimental results are presented, which confirm correct operation of the modulation strategy. [ABSTRACT FROM PUBLISHER]

Conventional matrix converters (MCs) have limited voltage gain that is less than 0.866, whether for direct MC (DMC) or indirect MC (IMC). Existing Z-source (ZS)/discontinuous quasi-Z-source (qZS) DMCs and ZS IMCs achieved larger than 0.866 voltage gain; however, the former inherited the complex commutation from DMC, and the latter involved a ZS network in dc link and led to non-all-silicon solution. In this paper, ZS and discontinuous qZS networks of existing ZS/qZS DMCs are used for an IMC topology for simplifying commutation and having high voltage gain, but they require extra input filter to reduce current harmonics. A new continuous qZS IMC is proposed, where a qZS network integrates the filtering function of the grid side; hence, additional input filter is avoided in the proposed continuous qZS IMC. Three new IMCs are compared in detail, in terms of voltage gain, current ripple, voltage ripple, inductor current and capacitor voltage stresses, ZS/qZS switch current and voltage stresses, filtering function, input current total harmonic distortion (THD), output voltage THD, and efficiency. Their control and modulation methods are presented to achieve the desired performances. Experimental comparisons verify the theoretical analysis and that the proposed continuous qZS IMC is a promising topology. [ABSTRACT FROM PUBLISHER]

Affected by the equivalent series resistance (ESR) of the devices in the circuit, the voltage-conversion ratio of traditional boost converter is limited. Various topologies have been developed to provide a high step-up voltage gain. An inherent high voltage gain can be achieved in a dual-switch converter with the advantages of low voltage and current stress on the switches. However, this converter has a strict requirement of the parameters' consistency. This paper discusses the steady-state operation principle of the converter in detail under the condition that the parameters are inconsistent and then illustrates the solutions to balance the voltage on the switches and suppress the resonance with passive lossless clamping. Finally, a prototype has been established in the laboratory, and simulation and experimental results have been given to verify the analysis and the effectiveness of clamping method. [ABSTRACT FROM PUBLISHER]

In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation. [ABSTRACT FROM PUBLISHER]